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参数资料
| 型号： | AS7C33512NTD18A-166BC |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 9 ns, PBGA119 |
| 封装： | 14 X 20 MM, BGA-119 |
| 文件页数： | 10/12页 |
| 文件大小： | 299K |
| 代理商： | AS7C33512NTD18A-166BC |
AS7C33512NTD16A
AS7C33512NTD18A
3/11/02;
v.1.8H
Alliance Semiconductor
7 of 12
Timing characteristics over operating range
Parameter
Symbol
-166 H
–166
–150
–133
–100
Unit Notes1
1 Refer to “notes” on page 10.
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock frequency
fMax
–
166
–
166
–
150
–
133
–
100 MHz
Cycle time (pipelined mode)
tCYC
6
–
6
–
6.6
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
tCYCF
10
–
10
–
10
–
12
–
12
–
ns
Clock access time (pipelined mode)- 3.3V VDDQ
tCD 3.3V
–3.0
–3.5
–3.8
–4.0
–5.0
ns
Clock access time (pipelined mode)- 2.5V VDDQ
tCD 2.5V
–4.0
–4.3
–4.5
–5.0
ns
Clock access time (flow-through mode)
tCDF
–9–9–
10
–
10
–
12
ns
Output enable LOW to data valid
tOE
–3.5
–3.8
–4.0
–5.0
ns
Clock HIGH to output Low Z
tLZC
0–
ns
2,3,4
Data output invalid from clock HIGH
tOH
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
tLZOE
0–
ns
2,3,4
Output enable HIGH to output High Z
tHZOE
–3.0
–3.5
–3.8
–4.0
–4.5
ns
2,3,4
Clock HIGH to output High Z
tHZC
–3.0
–3.5
–3.8
–4.0
–5.0
ns
2,3,4
Output enable HIGH to invalid output
tOHOE
0–
ns
Clock HIGH pulse width
tCH
2.4
–
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
tCL
2.4
–
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
tAS
1.2
–
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
tDS
1.2
–
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
tWS
1.2
–
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
tCSS
1.2
–
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,8
ADV/LD
setup to clock HIGH
tADVS
1.2
–
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Clock enable setup to clock HIGH
tCENS
1.2
–
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Address hold from clock HIGH
tAH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
tDH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
tWH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
tCSH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV/LD
hold from clock HIGH
tADVH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Clock enable hold from clock HIGH
tCENH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
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相关代理商/技术参数 |
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|---|---|
| AS7C33512NTD18A-166TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
| AS7C33512NTD18A-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD |
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