- 您现在的位置：买卖IC网 > PDF目录298831 > AS7C3364NTD36B-133TQIN (INTEGRATED SILICON SOLUTION INC) 64K X 36 ZBT SRAM, 4 ns, PQFP100 PDF资料下载
参数资料
| 型号： | AS7C3364NTD36B-133TQIN |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 64K X 36 ZBT SRAM, 4 ns, PQFP100 |
| 封装： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件页数： | 19/19页 |
| 文件大小： | 437K |
| 代理商： | AS7C3364NTD36B-133TQIN |
AS7C3364NTD32B
AS7C3364NTD36B
4/28/05; v.1.3
Alliance Semiconductor
P. 9 of 19
Snooze Mode Electrical Characteristics
Timing characteristics over operating range
Parameter
Sym
-200
-166
-133
Unit
Notes1
1 See “Notes” on page 15.
Min
Max
Min
Max
Min
Max
Clock frequency
fMAX
–
200
-
166
-
133
MHz
Cycle time
tCYC
5
–
6
-
7.5
-
ns
Clock access time
tCD
–
3.0
-
3.5
-
4.0
ns
Output enable Low to data valid
tOE
–
3.0
-
3.5
-
4.0
ns
Clock High to output Low Z
tLZC
0
–
0
-
0
-
ns
2,3,4
Data output invalid from clock High
tOH
1.5–1.5
-
1.5
-
ns
4
Output enable Low to output Low Z
tLZOE
0
–
0
-
0
-
ns
2,3,4
Output enable High to output High Z
tHZOE
–
3.0
-
3.5
-
4.0
ns
2,3,4
Clock High to output High Z
tHZC
–
3.0
-
3.5
-
4.0
ns
2,3,4
Clock High to output High Z
tHZCN
–
1.5
-
1.5
-
2.0
ns
5
Clock High pulse width
tCH
2.0–2.4
-
2.5
-
ns
6
Clock Low pulse width
tCL
2.3–2.4
-
2.5
-
ns
6
Address setup to clock High
tAS
1.4–1.5
-
1.5
-
ns
7
Data setup to clock High
tDS
1.4–1.5
-
1.5
-
ns
7
Write setup to clock High
tWS
1.4–1.5
-
1.5
-
ns
7
Chip select setup to clock High
tCSS
1.4–1.5
-
1.5
-
ns
7
Clock enable setup to clock High
tCENS
1.4–1.5
-
1.5
-
ns
7
ADV/LD
setup to clock High
tADVS
1.4–1.5
-
1.5
-
ns
7
Address hold from clock High
tAH
0.4–0.5
-
0.5
-
ns
7
Data hold from clock High
tDH
0.4–0.5
-
0.5
-
ns
7
Write hold from clock High
tWH
0.4–0.5
-
0.5
-
ns
7
ADV/LD
hold from clock High
tADVH
0.4–0.5
-
0.5
-
ns
7
Clock enable hold from clock High
tCENH
0.4–0.5
-
0.5
-
ns
7
Chip select hold from clock High
tCSH
0.4–0.5
-
0.5
-
ns
7
Description
Conditions
Symbol
Min
Max
Units
Current during Snooze Mode
ZZ > VIH
ISB2
30
mA
ZZ active to input ignored
tPDS
2cycle
ZZ inactive to input sampled
tPUS
2cycle
ZZ active to SNOOZE current
tZZI
2cycle
ZZ inactive to exit SNOOZE current
tRZZI
0cycle
相关PDF资料 |
PDF描述 |
|---|---|
| AS7C3364NTD36B-200TQC | 64K X 36 ZBT SRAM, 3 ns, PQFP100 |
| ASD15-12D15 | 2-OUTPUT 7.5 W DC-DC REG PWR SUPPLY MODULE |
| ASD75-48S5Q-N | 1-OUTPUT 75 W DC-DC REG PWR SUPPLY MODULE |
| ASE3-FREQ-D-Y-T | CRYSTAL OSCILLATOR, CLOCK, 0.5 MHz - 133 MHz, CMOS OUTPUT |
| ASE62G | SLIDE SWITCH, 6PDT, LATCHED, THROUGH HOLE-STRAIGHT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C3364NTD36B-166TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-166TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-166TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-200TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
发布紧急采购，3分钟左右您将得到回复。