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参数资料
| 型号： | AS7C3364NTD36B-133TQIN |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 64K X 36 ZBT SRAM, 4 ns, PQFP100 |
| 封装： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件页数： | 7/19页 |
| 文件大小： | 437K |
| 代理商： | AS7C3364NTD36B-133TQIN |
AS7C3364NTD32B
AS7C3364NTD36B
4/28/05; v.1.3
Alliance Semiconductor
P. 15 of 19
AC test conditions
Notes
Z0=50
Dout
50
VL=1.5V
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
VSS
90%
10%
+3.0V
Output Load: see Figure B,
except for tLZC, tLZOE, tHZOE, tHZC see Figure C.
Input pulse level: VSS to 3V. See Figure A.
Input rise and fall time (Measured at 0.3V and 2.7V): 1.0V/ns. See Figure A.
Input and output timing reference levels: 1.5V.
353
/ 1538
5 pF*
319
/ 1667
DOUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
1
For test conditions, see AC Test Conditions, Figures A, B, C.
2
This parameter measured with output load condition in Figure C
3
This parameter is sampled and not 100% tested.
4tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temper-
ature and voltage.
5
tHZCN is a ‘no load’ parameter to indicate exactly when SRAM outputs
have stopped driving.
6tCH measured as HIGH above VIH, and tCL measured as LOW below
VIL
7
This is a synchronous device. All addresses must meet the specified
setup and hold times for all rising edges of CLK. All other synchronous
inputs must meet the setup and hold times with stable logic levels for all
rising edges of CLK when chip is enabled.
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相关代理商/技术参数 |
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| AS7C3364NTD36B-166TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-166TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-166TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
| AS7C3364NTD36B-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Pipelined SRAM with NTD |
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