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参数资料
| 型号： | AT25256W-10SI-2.7 |
| 厂商： | Atmel |
| 文件页数： | 8/22页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256KBIT 3MHZ 8SOIC |
| 标准包装： | 94 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 2.1MHz，3MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
Table 9. WPEN Operation
Protected
Unprotected
Status
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Register
Protected
Writable
Protected
Protected
Protected
Writable
READ SEQUENCE (READ): Reading the AT25128/256 via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the READ op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10 on
page 9). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read,
the CS line should be driven high after the data comes out. The read sequence can be
continued since the byte address is automatically incremented and data will continue to
be shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE):
In order to program the AT25128/256, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to
select the device, the Write op-code is transmitted via the SI line followed by the byte
address and the data (D7 – D0) to be programmed (see Table 10 on page 9). Program-
ming will start after the CS pin is brought high. The low-to-high transition of the CS pin
must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status
Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,
the write cycle has ended. Only the RDSR instruction is enabled during the write pro-
gramming cycle.
8
AT25128/256
0872O–SEEPR–03/05
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相关代理商/技术参数 |
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| AT-252PIN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Attenuator |
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