参数资料
型号: AT32UC3A0256-ALUT
厂商: Atmel
文件页数: 83/97页
文件大小: 0K
描述: IC MCU AVR32 256KB FLASH 144LQFP
产品培训模块: AVR UC3 Audio Application
MCU Product Line Introduction
AVR EVK1105 Digital Audio Gateway Kit
AVR® UC3 Introduction
标准包装: 300
系列: AVR®32 UC3 A0
核心处理器: AVR
芯体尺寸: 32-位
速度: 66MHz
连通性: EBI/EMI,以太网,I²C,SPI,SSC,UART/USART,USB OTG
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 109
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP
包装: 托盘
配用: ATSTK600-RC33-ND - STK600 ROUTING CARD AVR
ATEVK1105-ND - KIT EVAL FOR AT32UC3A0
ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
84
AT32UC3A
15.5
Rev. E
15.5.1
SPI
1.
SPI FDIV option does not work
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
2.
SPI Slave / PDCA transfer: no TX UNDERRUN flag
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
3.
SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and
CNCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others
doesn’t equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on
SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrate equals to 1, the other must also equal 1
if CPOL=1 and CPHA=0.
4.
SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first
transfer
In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or
during the first transfer.
Fix/Workaround
1. Set slave mode, set required CPOL/CPHA.
2. Enable SPI.
3. Set the polarity CPOL of the line in the opposite value of the required one.
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
5.
SPI CSNAAT bit 2 in register CSR0...CSR3 is not available.
Fix/Workaround
Do not use this bit.
6.
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a Software Reset.
7.
SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and
NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
32058KS–AVR32–01/12
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