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参数资料
| 型号： | AT45DB081B-TU |
| 厂商： | Atmel |
| 文件页数： | 4/33页 |
| 文件大小： | 0K |
| 描述： | IC FLASH 8MBIT 20MHZ 28TSOP |
| 标准包装： | 234 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | DataFLASH |
| 存储容量： | 8M（4096 页 x 264 字节） |
| 速度： | 20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-TSSOP（0.465"，11.8mm 宽） |
| 供应商设备封装： | 28-TSOP |
| 包装： | 托盘 |
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downward compatibility to larger and smaller density devices (see Notes under “Command
Sequence for Read/Write Operations” diagram). The next 12 address bits (PA11 - PA0) specify
which page of the main memory array to read, and the last nine bits (BA8 - BA0) of the 24-bit
address sequence specify the starting byte address within the page. The 32 don’t care bits that
follow the 24 address bits are needed to initialize the read operation. Following the 32 don’t care
bits, additional clock pulses on the SCK pin will result in serial data being output on the SO
(serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a Con-
tinuous Array Read, the device will continue reading at the beginning of the next page with no
delays incurred during the page boundary crossover (the crossover from the end of one page to
the beginning of the next page). When the last bit in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with crossing
over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the f CAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data directly
from any one of the 4096 pages in the main memory, bypassing both of the data buffers and
leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H
must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first
three bits of the 24-bit address sequence are reserved bits, the next 12 address bits (PA11 -
PA0) specify the page address, and the next nine address bits (BA8 - BA0) specify the starting
byte address within the page. The 32 don’t care bits which follow the 24 address bits are sent to
initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in
serial data being output on the SO (serial output) pin. The CS pin must remain low during the
loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the
end of a page in main memory is reached during a Main Memory Page Read, the device will
continue reading at the beginning of the same page. A low-to-high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to
specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1,
and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the
eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t
care bits. Since the buffer size is 264 bytes, nine address b its (BFA8 - BFA0) are required to
specify the first byte of data to be read from the buffer. The CS pin must remain low during the
loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the
end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ: The status register can be used to determine the device ’s
Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting
with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five
most significant bits of the status register will contain device information, while the remaining
three least-significant bits are reserved for future use and will have undefined values. After bit 0
of the status register has been shifted out, the sequence will repeat itself (as long as CS remains
4
AT45DB081B
2225J–DFLSH–2/08
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AT45DB081D | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081D_07 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081D_08 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081D_09 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-megabit 2.5-volt or 2.7-volt DataFlash |
| AT45DB081D_13 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-megabit 2.5V or 2.7V DataFlash |
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