参数资料
型号: AT49BV8192AT
厂商: Atmel Corp.
英文描述: 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
中文描述: 8兆100万× 8 /为512k × 16的CMOS闪存
文件页数: 5/16页
文件大小: 246K
代理商: AT49BV8192AT
AT49BV008A(T)/8192A(T)
5
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49BV008A(T)/8192A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
TOGGLE BIT:
In addition to DATA polling the
AT49BV008A(T)/8192A(T) provides another method for
determining the end of a program or erase cycle. During a
program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
READY/BUSY:
For the AT49F008A(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49BV008A(T)/8192A(T) in the following ways: (a) V
CC
sense: if V
CC
is below 1.8V (typical), the program function
is inhibited. (b) V
CC
power on delay: once V
CC
has reached
the V
CC
sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS:
While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
CC
+ 0.6V.
AT49BV008A(T) ALTERNATE PIN DEFINITION:
Two
AT49BV008A(T) BGA pin definitions are shown. The stan-
dard pin definition allows use of the JEDEC standard pro-
gramming algorithm. If the alternate pin definition is used,
the programming algorithm must be modified as shown in
the Command Definition for Alternate Pin Definition Table
on page 7.
相关PDF资料
PDF描述
AT49BV8192AT-12CC 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
AT49BV8192AT-12CI 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
AT49BV8192AT-12TC 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
AT49BV8192AT-12TI 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
AT49BV8192AT-15CC 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
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AT49BV8192AT-11TI 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM|FLASH|512KX16/1MX8|CMOS|TSSOP|48PIN|PLASTIC
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