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参数资料
| 型号： | AT49SV12804-70TI |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 128-megabit (8M x 16) Burst/Page Mode 1.8-volt Flash Memory |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 70 ns, PDSO56 |
| 封装： | 14 X 20 MM, PLASTIC, M0-142EC, TSOP1-56 |
| 文件页数： | 3/41页 |
| 文件大小： | 397K |
| 代理商： | AT49SV12804-70TI |
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3
AT49SN/SV12804 [Preliminary]
3314A–FLASH–4/04
Device
Operation
COMMAND SEQUENCES:
When the device is first powered on, it will be in the read mode.
Command sequences are used to place the device in other operating modes such as program
and erase. The command sequences are written by applying a low pulse on the WE input with
CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE
high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by
a low-to-high transition on the AVD signal. If the AVD is not pulsed low, the address will be
latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the
WE or the CE pulse, whichever occurs first. The addresses used in the command sequences
are not affected by entering the command sequences.
BURST CONFIGURATION COMMAND:
The Program Burst Configuration Register command
is used to program the burst configuration register. The burst configuration register determines
several parameters that control the read operation of the device. Bit B15 determines whether
synchronous burst reads are enabled or asynchronous reads are enabled. Since the page
read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to
enable the page read feature. Bit B14 determines whether a four-word page or an eight-word
page will be used. The rest of the bits in the burst configuration register are used only for the
burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency
for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock
latency versus input clock frequency table is shown on page 20. The “Burst Read Waveform”
as shown on page 31 illustrates a clock latency of four; the data is output from the device four
clock cycles after the first valid clock edge following the high-to-low AVD edge. The B10 bit of
the configuration register determines the polarity of the WAIT signal. The B9 bit of the burst
configuration register determines the number of clocks that data will be held valid (see Figure
4). The Hold Data for 2 Clock Cycles Read Waveform is shown on page 31. The clock latency
is not affected by the value of the B9 bit. The B8 bit of the burst configuration register deter-
mines when the WAIT signal will be asserted. When synchronous burst reads are enabled, a
linear burst sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and
the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of
the burst configuration register determine whether a continuous or fixed-length burst will be
used and also determine whether a four-, eight- or sixteen-word length will be used in the
fixed-length mode. When a four-, eight- or sixteen-word burst length is selected, Bit B3 can be
used to select whether burst accesses wrap within the burst length boundary or whether they
cross word length boundaries to perform linear accesses (see Table 5). All other bits in the
burst configuration register should be programmed as shown on page 20. The default state
(after power-up or reset) of the burst configuration register is also shown on page 20.
ASYNCHRONOUS READ:
There are two types of asynchronous reads – AVD pulsed and
standard asynchronous reads. The AVD pulsed read operation of the device is controlled by
CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE
is high. This dual-line control gives designers flexibility in preventing bus contention. The data
at the address location defined by A0 - A22 and captured by the AVD signal will be read when
CE and OE are low. The address location passes into the device when CE and AVD are low;
the address is latched on the low-to-high transition of AVD. Low input levels on the OE and CE
pins allow the data to be driven out of the device. The access time is measured from stable
address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD
pulsed read, the CLK signal may be static high or static low. For standard asynchronous
reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are
shown on page 28.
PAGE READ:
The page read operation of the device is controlled by CE, OE, and AVD inputs.
The CLK input is ignored during a page read operation and should be tied to GND. The page
size can be four words (default value) or eight words depending on what value bit B14 of the
burst configuration register is programmed to. During a page read, the AVD signal can transi-
tion low and then transition high, transition low and remain low, or can be tied to GND. If a high
to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the
相关PDF资料 |
PDF描述 |
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| AT49SN6416-70CI | 64-megabit (4M x 16) Burst/Page Mode 1.8-volt Flash Memory |
| AT49SN6416T | 64-megabit (4M x 16) Burst/Page Mode 1.8-volt Flash Memory |
| AT49SN6416T-70CI | 64-megabit (4M x 16) Burst/Page Mode 1.8-volt Flash Memory |
| AT49SN6416 | 64-megabit (4M x 16) Burst/Page Mode 1.8-volt Flash Memory |
| AT49SV322A | 32-megabit (2M x 16/4M x 8) 1.8-volt Only Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT49SV163D-80CU | 功能描述:闪存 Parallel 闪存 1.8V 80NS RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT49SV163D-80TU | 功能描述:闪存 Parallel 闪存 1.8V 80NS RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT49SV163DT-80CU | 功能描述:闪存 Parallel 闪存 1.8V 80NS, GR RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT49SV163DT-80TU | 功能描述:闪存 Parallel 闪存 1.8V 80NS, GR RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT49SV322A-80CU | 制造商:Atmel Corporation 功能描述:Flash Parallel 1.8V 32Mbit 4M/2M x 8bit/16bit 80ns 48-Pin CBGA |
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