参数资料
| 型号： | AT80C51RA2-SLSUL |
| 厂商： | Atmel |
| 文件页数： | 56/84页 |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU ROMLESS 44PLCC |
| 标准包装： | 972 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 30/20MHz |
| 连通性： | UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
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2007-2012 Microchip Technology Inc.
DS70292G-page 61
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.4.1
SOFTWARE STACK
In addition to its use as a working register, the W15
register
in
the
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices is also used as a software Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-6. For a PC push
during any CALL instruction, the MSb of the PC is zero-
extended before the push, ensuring that the MSb is
always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap does not occur. The stack error trap occurs on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x2000 in RAM, initialize the SPLIM with the value
0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
CALL STACK FRAME
4.4.2
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
4.5
Instruction Addressing Modes
The addressing modes shown in Table 4-37 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.5.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.5.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where:
Operand 1 is always a working register (that is, the
addressing mode can only be register direct), which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The fol-
lowing addressing modes are supported by MCU
instructions:
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
0
15
W15 (before CALL)
W15 (after CALL)
S
ta
ck
Gr
ow
sT
o
war
d
H
igh
er
A
ddr
es
s
0x0000
PC<22:16>
POP : [--W15]
PUSH : [W15++]
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
相关PDF资料 |
PDF描述 |
|---|---|
| AT80C51RA2-RLTUM | IC 8051 MCU ROMLESS 44VQFP |
| 213931-5 | CONN JACKSCREW RECEPT 34 POS |
| AT80C51RA2-RLTUL | IC 8051 MCU ROMLESS 44VQFP |
| AT80C51RA2-3CSUM | IC 8051 MCU ROMLESS 40DIP |
| AT80C51RA2-3CSUL | IC 8051 MCU ROMLESS 40DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT80C51RA2-SLSUM | 功能描述:8位微控制器 -MCU RLESS RA 40MHZ 5V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| AT80C51RB2-3CSCM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-3CSIM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-3CSUM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RB2-RLTIL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
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