参数资料
型号: AT89C51AC3-SLSIM
厂商: Atmel
文件页数: 129/140页
文件大小: 0K
描述: IC 8051 MCU FLASH 64K 44PLCC
标准包装: 27
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 60MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
2009 Microchip Technology Inc.
DS70286C-page 87
dsPIC33FJXXXGPX06/X08/X10
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
U-0
SFTACERR
DIV0ERR
DMACERR
MATHERR
ADDRERR
STKERR
OSCFAIL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
NSTDIS: Interrupt Nesting Disable bit
1
= Interrupt nesting is disabled
0
= Interrupt nesting is enabled
bit 14
OVAERR: Accumulator A Overflow Trap Flag bit
1
= Trap was caused by overflow of Accumulator A
0
= Trap was not caused by overflow of Accumulator A
bit 13
OVBERR: Accumulator B Overflow Trap Flag bit
1
= Trap was caused by overflow of Accumulator B
0
= Trap was not caused by overflow of Accumulator B
bit 12
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1
= Trap was caused by catastrophic overflow of Accumulator A
0
= Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1
= Trap was caused by catastrophic overflow of Accumulator B
0
= Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE: Accumulator A Overflow Trap Enable bit
1
= Trap overflow of Accumulator A
0
= Trap disabled
bit 9
OVBTE: Accumulator B Overflow Trap Enable bit
1
= Trap overflow of Accumulator B
0
= Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1
= Trap on catastrophic overflow of Accumulator A or B enabled
0
= Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1
= Math error trap was caused by an invalid accumulator shift
0
= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1
= Math error trap was caused by a divide by zero
0
= Math error trap was not caused by a divide by zero
bit 5
DMACERR: DMA Controller Error Status bit
1
= DMA controller error trap has occurred
0
= DMA controller error trap has not occurred
bit 4
MATHERR: Arithmetic Error Status bit
1
= Math error trap has occurred
0
= Math error trap has not occurred
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