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参数资料
型号： AT89C51RD2-SLRUM
厂商： Atmel
文件页数： 118/137页
文件大小： 0K
描述： IC MCU FLASH 8051 EEP 64K 44PLCC
产品培训模块： MCU Product Line Introduction
标准包装： 1
系列： 89C
核心处理器： 8051
芯体尺寸： 8-位
速度： 60MHz
连通性： SPI，UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 34
程序存储器容量： 64KB（64K x 8）
程序存储器类型： 闪存
RAM 容量： 2K x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 44-LCC（J 形引线）
包装： 标准包装
配用： AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
其它名称： AT89C51RD2-SLRUMDKR
81
4235K–8051–05/08
AT89C51RD2/ED2
18.3
Power-Down Mode
The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down
mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering
Power-Down mode is preserved, i.e., the program counter, program status word register retain
their data for the duration of Power-Down mode. In addition, the SFR and RAM contents are pre-
served. The status of the Port pins during Power-Down mode is detailed in Table 18-1.
Note:
VCC may be reduced to as low as VRET during Power-Down mode to further reduce power dissi-
pation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.
18.3.1
Entering Power-Down Mode
To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the
Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets
PD bit is the last instruction executed.
18.3.2
Exiting Power-Down Mode
Note:
If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is
restored to the normal operating level.
There are three ways to exit the Power-Down mode:
1.
Generate an enabled external interrupt.
– The AT89C51RD2/ED2 provides capability to exit from Power-Down using INT0#,
INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTx# input, execution resumes when the
input is released (see Figure 18-1). Execution resumes with the interrupt service
routine. Upon completion of the interrupt service routine, program execution
resumes with the instruction immediately following the instruction that activated
Power-Down mode.
Note:
The external interrupt used to exit Power-Down mode must be configured as level sensitive
(INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the inter-
rupt must be long enough to allow the oscillator to stabilize. The execution will only resume when
the interrupt is deasserted.
Note:
Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
Figure 18-1. Power-Down Exit Waveform Using INT1:0#
2.
Generate a reset.
– A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-Down mode and may
INT1:0#
OSC
Power-down phase
Oscillator restart phase
Active phase
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