参数资料
型号: AT89C51RD2-SLRUM
厂商: Atmel
文件页数: 69/137页
文件大小: 0K
描述: IC MCU FLASH 8051 EEP 64K 44PLCC
产品培训模块: MCU Product Line Introduction
标准包装: 1
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 60MHz
连通性: SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 标准包装
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
其它名称: AT89C51RD2-SLRUMDKR
37
4235K–8051–05/08
AT89C51RD2/ED2
Table 13-1.
CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Reset Value = 00XX X000b
Not bit addressable
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)
and each module (Refer to Table 13-2).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this
bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and
are set by hardware when either a match or a capture occurs. These flags also can only be
cleared by software.
7
6
5
4
3
2
1
0
CIDL
WDTE
-
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic
Description
7
CIDL
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6
WDTE
Watchdog Timer Enable
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
CPS1
PCA Count Pulse Select
CPS1CPS0
Selected PCA input
0
Internal clock F
CLK PERIPH/6
0
1
Internal clock F
CLK PERIPH/2
1
0
Timer 0 Overflow
1
External clock at ECI/P1.2 pin (max rate = F
CLK PERIPH/4)
1
CPS0
0
ECF
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
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