参数资料
型号: AT90USB1287-MUR
厂商: Atmel
文件页数: 26/106页
文件大小: 0K
描述: MCU AVR 128K FLASH 16MHZ 64QFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 1,000
系列: AVR® 90USB
核心处理器: AVR
芯体尺寸: 8-位
速度: 16MHz
连通性: EBI/EMI,I²C,SPI,UART/USART,USB,USB OTG
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 48
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 带卷 (TR)
26
7593L–AVR–09/12
AT90USB64/128
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEPE is cleared.
Bit 2 – EEMPE: EEPROM Master Programming Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the
selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEPE bit for an EEPROM write procedure.
Bit 1 – EEPE: EEPROM Programming Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-
wise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1.
Wait until EEPE becomes zero.
2.
Wait until SELFPRGEN in SPMCSR becomes zero.
3.
Write new EEPROM address to EEAR (optional).
4.
Write new EEPROM data to EEDR (optional).
5.
Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6.
Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Memory pro-
gramming” on page 359 for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
Table 6-2.
EEPROM Mode bits.
EEPM1
EEPM0
Programming
time
Operation
0
3.4ms
Erase and Write in one operation (atomic operation)
0
1
1.8ms
Erase only
1
0
1.8ms
Write only
11
Reserved for future use
相关PDF资料
PDF描述
AT90USB1287-AUR MCU AVR 128K FLASH 16MHZ 64TQFP
VE-BTF-IX CONVERTER MOD DC/DC 72V 75W
VI-B3X-IX-F2 CONVERTER MOD DC/DC 5.2V 75W
VE-BTF-IW CONVERTER MOD DC/DC 72V 100W
VI-B3X-IW-F4 CONVERTER MOD DC/DC 5.2V 100W
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