参数资料
型号: AT90USB82-16MUR
厂商: Atmel
文件页数: 8/38页
文件大小: 0K
描述: MCU AVR USB 8K FLASH 32-QFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 5,000
系列: AVR® 90USB
核心处理器: AVR
芯体尺寸: 8-位
速度: 16MHz
连通性: EBI/EMI,PS/2,SPI,UART/USART,USB
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATSTK526-ND - KIT STARTER FOR AT90USB82/162
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
16
7707F–AVR–11/10
AT90USB82/162
5.
AVR AT90USB82/162 Memories
This section describes the different memories in the AT90USB82/162. The AVR architecture has
two main memory spaces, the Data Memory and the Program Memory space. In addition, the
AT90USB82/162 features an EEPROM Memory for data storage. All three memory spaces are
linear and regular.
5.1
In-System Reprogrammable Flash Program Memory
The AT90USB82/162 contains 8K / 16K bytes On-chip In-System Reprogrammable Flash mem-
ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
as 4K x 16, 8K x 16. For software security, the Flash Program memory space is divided into two
sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 100,000 write/erase cycles. The
AT90USB82/162 Program Counter (PC) is 16 bits wide, thus addressing the 8K / 16K program
memory locations. The operation of Boot Program section and associated Boot Lock bits for
software protection are described in detail in “Memory Programming” on page 243. “Memory
Programming” on page 243 contains a detailed description on Flash data serial downloading
using the SPI pins or the debugWIRE interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description and ELPM - Extended Load Program Memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
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