参数资料
型号: AT91SAM7S256C-MU
厂商: Atmel
文件页数: 91/165页
文件大小: 0K
描述: IC ARM7 MCU 32BIT 256K 64QFN
标准包装: 260
系列: SAM7S
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 55MHz
连通性: I²C,SPI,SSC,UART/USART,USB
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 托盘
31
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
9.5
Debug Unit
Comprises:
One two-pin UART
One Interface for the Debug Communication Channel (DCC) support
One set of Chip ID Registers
One Interface providing ICE Access Prevention
Two-pin UART
Implemented features are compatible with the USART
Programmable Baud Rate Generator
Parity, Framing and Overrun Error
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Debug Communication Channel Support
Offers visibility of COMMRX and COMMTX signals from the ARM Processor
Chip ID Registers
Identification of the device revision, sizes of the embedded memories, set of peripherals
Chip ID is 0x270B0A40 for AT91SAM7S512 Rev A
Chip ID is 0x270B0A4F for AT91SAM7S512 Rev B
Chip ID is 0x270D0940 for AT91SAM7S256 Rev A
Chip ID is 0x270B0941 for AT91SAM7S256 Rev B
Chip ID is 0x270B0942 for AT91SAM7S256 Rev C
Chip ID is 0x270B0943 for AT91SAM7S256 Rev D
Chip ID is 0x270C0740 for AT91SAM7S128 Rev A
Chip ID is 0x270A0741 for AT91SAM7S128 Rev B
Chip ID is 0x270A0742 for AT91SAM7S128 Rev C
Chip ID is 0x270A0743 for AT91SAM7S128 Rev D
Chip ID is 0x27090540 for AT91SAM7S64 Rev A
Chip ID is 0x27090543 for AT91SAM7S64 Rev B
Chip ID is 0x27090544 for AT91SAM7S64 Rev C
Chip ID is 0x27080342 for AT91SAM7S321 Rev A
Chip ID is 0x27080340 for AT91SAM7S32 Rev A
Chip ID is 0x27080341 for AT91SAM7S32 Rev B
Chip ID is 0x27050241 for AT9SAM7S161 Rev A
Chip ID is 0x27050240 for AT91SAM7S16 Rev A
Note:
Refer to the errata section of the datasheet for updates on chip ID.
9.6
Periodic Interval Timer
20-bit programmable counter plus 12-bit interval counter
9.7
Watchdog Timer
12-bit key-protected Programmable Counter running on prescaled SCLK
Provides reset or interrupt signals to the system
Counter may be stopped while the processor is in debug state or in idle mode
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