参数资料
型号: AT91SAM7S32B-MU-999
厂商: Atmel
文件页数: 147/165页
文件大小: 0K
描述: IC MCU ARM7 32KB FLASH 48-VQFN
产品培训模块: MCU Product Line Introduction
标准包装: 3,500
系列: SAM7S
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 55MHz
连通性: I²C,SPI,SSC,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 21
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 带卷 (TR)
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
82
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
15.3
Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a
20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the
Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic
Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, pro-
vided the interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the over-
flow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives
the number of periodic intervals elapsed since the last read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no
effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without
clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit
only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit
is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts count-
ing, only if the PITEN is set again.
The PIT is stopped when the core enters debug state.
Figure 15-2. Enabling/Disabling PIT with PITEN
MCK Prescaler
PIV
PIV - 1
0
PITEN
10
0
15
CPIV
1
restarts MCK Prescaler
0
1
APB cycle
read PIT_PIVR
0
PICNT
PITS (PIT_SR)
MCK
APB Interface
APB cycle
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