参数资料
型号: AT91SAM9G20B-CU
厂商: Atmel
文件页数: 14/42页
文件大小: 0K
描述: IC ARM9 MPU 217-LFBGA
产品培训模块: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
标准包装: 126
系列: SAM9G
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 400MHz
连通性: EBI/EMI,以太网,I²C,IrDA,ISI,MMC,SPI,SSC,UART/USART,USB
外围设备: DMA,POR,PWM,WDT
输入/输出数: 96
程序存储器容量: 64KB(64K x 8)
程序存储器类型: ROM
RAM 容量: 96K x 8
电压 - 电源 (Vcc/Vdd): 0.9 V ~ 1.1 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 217-LFBGA
包装: 托盘
配用: AT91SAM9G20-EK-ND - KIT EVAL FOR AT91SAM9G20 MCU
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
其它名称: AT91SAM9G20-CU
AT91SAM9G20-CU-ND
21
6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 19.
The AT91SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin
at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved
for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
8.1.1.1
BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
Boot on slow clock (On-chip RC or 32,768 Hz)
Auto baudrate detection
Downloads and runs an application from external storage media into internal SRAM
Downloaded code size depends on embedded SRAM size
Automatic detection of valid application
Bootloader on a non-volatile memory
– SDCard (boot ROM does not support high capacity SDCards.)
–NAND Flash
– SPI DataFlash and Serial Flash connected on NPCS0 and NPCS1 of the SPI0
– EEPROM on TWI
SAM-BA
Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device HS Port
8.1.1.2
BMS = 0, Boot on External Memory
Boot on slow clock (On-chip RC or 32,768 Hz)
Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
1.
Program the PMC (main oscillator enable or bypass mode).
2.
Program and start the PLL.
3.
Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock.
4.
Switch the main clock to the new value.
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