参数资料
| 型号： | ATTINY15L-1PU |
| 厂商： | Atmel |
| 文件页数： | 15/85页 |
| 文件大小： | 0K |
| 描述： | IC MCU AVR 1K FLASH 1.6MHZ 8-DIP |
| 标准包装： | 50 |
| 系列： | AVR® ATtiny |
| 核心处理器： | AVR |
| 芯体尺寸： | 8-位 |
| 速度： | 1.6MHz |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 6 |
| 程序存储器容量： | 1KB（512 x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 64 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 4x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
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22
ATtiny15L
1187H–AVR–09/07
Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0
(T im er/Co u n t er0 Ove r flow Inte rrup t En able) an d TO V0 a r e set (o ne) , th e
Timer/Counter0 Overflow interrupt is executed.
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
External Interrupt
The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt
will trigger even if the INT0 pin is configured as an output. This feature provides a way of
generating a software interrupt. The External Interrupt can be triggered by a falling or
rising edge, a pin change, or a low level. This is set up as indicated in the specification
for the MCU Control Register (MCUCR). When the external interrupt is enabled and is
configured as level-triggered, the interrupt will trigger as long as the pin is held low.
The External Interrupt is set up as described in the specification for the MCU Control
Register (MCUCR).
Pin Change Interrupt
The pin change interrupt is triggered by any change in logical value on any input or I/O
pin. Change on pins PB4..0 will always cause an interrupt. Change on pin PB5 will
cause an interrupt if the pin is configured as input or I/O, as described in the section “Pin
Descriptions” on page 4. Observe that, if enabled, the interrupt will trigger even if the
changing pin is configured as an output. This feature provides a way of generating a
software interrupt. Also observe that the pin change interrupt will trigger even if the pin
activity triggers another interrupt, for example the external interrupt. This implies that
one external event might cause several interrupts. The values on the pins are sampled
before detecting edges. If pin change interrupt is enabled, pulses that last longer than
one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt.
The MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bits 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit 6- PUD: Pull-up Disable
This PUD bit must be set (one) to disable internal pull-up registers at Port B.
Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
Bit
7654
321
0
$35
–
PUD
SE
SM1
SM0
–
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R
R/W
Initial Value
0000
000
0
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| ATTINY15L-1SC | 功能描述:8位微控制器 -MCU AVR 1K FLASH 64B EE ADC 3V 1.6MHZ RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ATTINY15L-1SC SL383 | 制造商:Atmel Corporation 功能描述:MCU 8-Bit ATtiny AVR RISC 1KB Flash 3.3V/5V 8-Pin SOIC EIAJ T/R |
| ATTINY15L-1SI | 功能描述:8位微控制器 -MCU AVR 1K FLASH 64B EE ADC 3V 1.6MHZ RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ATTINY15L-1SI SL383 | 制造商:Atmel Corporation 功能描述:MCU 8-bit ATtiny AVR RISC 1KB Flash 3.3V/5V 8-Pin SOIC EIAJ T/R |
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