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| 型号： | AX125-1CS180I |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1344 CLBS, 82000 GATES, 763 MHz, PBGA180 |
| 封装： | 0.80 MM PITCH, CSP-180 |
| 文件页数： | 7/230页 |
| 文件大小： | 6485K |
| 代理商： | AX125-1CS180I |
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Axcelerator Family FPGAs
2- 90
v2.8
Instruction Register (IR) and the Data Registers (such as
BSR,
IDCODE,
USRCODE,
BYPASS,
etc.).
The
TAP
Controller steps into one of the states depending on the
sequence of TMS at the rising edges of TCK.
Instruction Register (IR)
The IR has five bits (IR4 to IR0). At the TRST state, IR is
reset to IDCODE. Each time when IR is selected, it goes
through "select IR-Scan," "Capture-IR," "Shift-IR," all the
way through "Update-IR." When there is no test error,
the first five data bits coming out of TDO during the
"Shift-IR" will be "10111." If a test error occurs, the last
three bits will contain one to three zeroes corresponding
to
negatively
asserted
signals:
"TDO_ERRORB,"
"PROBA_ERRORB," and "PROBB_ERRORB." The error(s)
will be erased when the TAP is at the "Update-IR" or the
TRST state. When in user mode start-up sequence, if the
micro-probe has not been used, the "PROBA_ERRORB" is
used as a "Power-up done successfully" flag.
Data Registers (DRs)
Data registers are distributed throughout the chip. They
store testing/programming vectors. The MSB of a data
register is connected to TDI, while the LSB is connected
to TDO. There are different types of data registers.
Descriptions of the main registers are as follow:
1. IDCODE:
The IDCODE is a 33-bit hard coded JTAG Silicon
Signature. It is a hardwired device ID code, which
contains the Actel identity, part number, and version
number in a specific JTAG format.
2. USERCODE:
The USERCODE is a 32-bit programmable JTAG Silicon
Signature. It is a supplementary identity code for the
user to program information to distinguish different
programmed parts. USERCODE fuses will read out as
"zeroes" when not programmed, so only the "1" bits
need to be programmed.
3. Boundary-Scan Register (BSR):
Each I/O contains three Boundary-Scan Cells. Each cell
has a shift register bit, a latch, and two MUXes. The
boundary-scan cells are used for the Output-enable
(E), Output (O), and Input (I) registers. The bit order
of the boundary-scan cells for each of them is E-O-I.
The boundary-scan cells are then chained serially to
form the Boundary-Scan Register (BSR). The length of
the BSR is the number of I/Os in the die multiplied by
three.
4. Bypass Register (BYR):
This is the "1-bit" register. It is used to shorten the
TDI-TDO serial chain in board-level testing to only
one bit per device not being tested. It is also selected
for all "reserved" or unused instructions.
Probing
Internal activities of the JTAG interface can be observed
via the Silicon Explorer II probes: "PRA," "PRB," "PRC,"
and "PRD."
Special Fuses
Security
Actel antifuse FPGAs, with FuseLock technology, offer
the highest level of design security available in a
programmable logic device. Since antifuse FPGAs are
live-at power-up, there is no bitstream that can be
intercepted, and no bitstream or programming data is
ever downloaded to the device during power-up, thus
making device cloning impossible.
In addition, special
security fuses are hidden throughout the fabric of the
device and may be programmed by the user to thwart
attempts to reverse engineer the device by attempting
to exploit either the programming or probing interfaces.
Both invasive and noninvasive attacks against an
Axcelerator device that access or bypass these security
fuses will destroy access to the rest of the device. (refer
FPGAs white paper).
Look for this symbol to ensure your valuable IP is secure.
To ensure maximum security in Axcelerator devices, it is
recommended that the user program the device security
fuse (SFUS). When programmed, the Silicon Explorer II
testing probes are disabled to prevent internal probing,
and the programming interface is also disabled. All JTAG
public instructions are still accessible by the user.
For more information, refer to Actel’s Implementation of
Security in Actel Antifuse FPGAs application note.
Global Set Fuse
The Global Set Fuse determines if all R-cells and I/O
registers (InReg, OutReg, and EnReg) are either cleared
or preset by driving the GCLR and GPSET inputs of all R-
cells and I/O Registers (Figure 2-31 on page 2-47). Default
setting is to clear all registers (GCLR = 0 and GPSET =1) at
device power-up. When the GBSETFUS option is checked
during FUSE file generation, all registers are preset
(GCLR = 1 and GPSET= 0). A local CLR or PRESET will take
precedence over this setting. Both pins are pulled High
during normal device operation. For use details, see the
Libero IDE online help.
Figure 2-69 FuseLock Logo
e
u
相关PDF资料 |
PDF描述 |
|---|---|
| AX125-1CS180 | FPGA, 1344 CLBS, 82000 GATES, 763 MHz, PBGA180 |
| AX125-1FG256I | FPGA, 1344 CLBS, 82000 GATES, 763 MHz, PBGA256 |
| AX125-1FG256 | FPGA, 1344 CLBS, 82000 GATES, 763 MHz, PBGA256 |
| AX125-1FG324I | FPGA, 1344 CLBS, 82000 GATES, 763 MHz, PBGA324 |
| AX125-1FG324 | FPGA, 1344 CLBS, 82000 GATES, 763 MHz, PBGA324 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AX125-1CS896 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX125-1CS896B | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX125-1CS896I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX125-1CS896M | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX125-1CS896PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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