参数资料
型号: BD9011KV-E2
厂商: Rohm Semiconductor
文件页数: 4/30页
文件大小: 0K
描述: IC REG CTRLR BST PWM 48-VQFP
标准包装: 1
PWM 型: 控制器
输出数: 2
频率 - 最大: 550kHz
电源电压: 3.9 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 标准包装
产品目录页面: 1373 (CN2011-ZH PDF)
其它名称: BD9011KV-E2DKR
● Block diagram
(Parentheses indicate VQFP48C pin numbers)
EXTVCC
STB VCC
RT
SYNC
22
(41)
10
(25)
32
(7)
15
(33)
16
(34)
5V Reg
VREG5
24(44)
3.3V Reg
5(19)
VREG33
B.G
SYNC
17(35)
LLM
VCCCL2
31(5)
2.7V
UVLO
TSD
TSD
OSC
33(8)
VCCCL1
CL2
30(3)
34(10)
CL1
BOOT2
29(2)
OCP
OCP
35(11)
BOOT1
OUTH2
SW2
28(1)
27(48)
SW
Set
DRV
Reset
Set
Reset
DRV
SW
36(12)
1(13)
OUTH1
SW1
VREG5
LOGIC
TSD
UVLO
TSD
UVLO
LOGIC
4(17)
VREG5A
OUTL2
25(46)
Q
Reset Set
PW M
COMP
Slope
Slope
PW M
COMP
Q
Set Reset
3(15)
OUTL1
DGND2
26(47)
2(14)
DGND1
FB2
SS2
COMP2
21(39)
19(37)
20(38)
0.8V
Err Amp
UVLO
Err Amp
0.8V
6(21)
8(23)
7(22)
FB1
SS1
COMP1
Set
Q
Reset
Q
Reset
Set
Sequence DET
Sequence DET
0.56V
0.56V
18
(36)
14
(31)
12
(27)
11
(26)
(30)
13
(29)
9
(24)
DET2
LOFF
EN2
EN1 (GNDS) GND
DET1
Fig-13
● Pin configuration
● PIN function table
BD9011EKN ( HQFN36V )
Pin
No.
1
2
3
4
Pin name
SW1
DGND1
OUTL1
VREG5A
Function
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
FET drive REG input
27
26
25
24
23
22
21
20
19
5
6
VREG33
FB1
Reference input REG output
Error amp input 1
7
COMP1
Error amp output 1
OUTH2 28
BOOT2 29
CL2 30
VCCCL2 31
VCC 32
VCCCL1 33
CL1 34
BOOT1 35
OUTH1 36
18 DET2
17 LMM
16 SYNC
15 RT
14 LOFF
13 GND
12 EN2
11 EN1
10 STB
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SS1
DET1
STB
EN1
EN2
GND
LOFF
RT
SYNC
LLM
DET2
SS2
COMP2
FB2
Soft start setting pin 1
FB detector output 1
Standby ON/OFF pin
Output 1ON/OFF pin
Output 2ON/OFFpin
Ground
Over current protection OFF latch
function ON/OFF pin
Switching frequency setting pin
External synchronous pulse input pin
Built-in pull-down resistor pin
FB detector output 2
Soft start setting pin 2
Error amp output 2
Error amp input 2
1
2
3
4
5
6
7
8
9
22
EXTVCC
External power input pin
23
24
25
26
27
VREG5
OUTL2
DGND2
SW2
N.C.
FET drive REG output
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
Fig-14
28
29
30
31
32
33
34
35
36
OUTH2
BOOT2
CL2
VCCCL2
VCC
VCCCL1
CL1
BOOT1
OUTH1
Hi side FET gate drive pin 2
OUTH2 driver power pin
Over current detector setting pin 2
Over current detection VCC2
Input power pin
Over current detection VCC1
Over current detector setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
4/29
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