参数资料
| 型号： | BD9302FP-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A DL HSOP25 |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 14.4 V |
| 输入电压： | 6 V ~ 18 V |
| 频率 - 开关： | 200kHz ~ 2.5MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 25-SOP（0.213"，5.40mm）+ 2 翼片 |
| 包装： | 标准包装 |
| 供应商设备封装： | 25-HSOP |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9302FP-E2DKR |
For output capacitors having high ESR, such as aluminum electrolytic capacitor
For output capacitors having high ESR (i.e., several ohms), the phase compensation setting procedure becomes
comparatively simple. Since the DC/DC converter application has surely a LC resonant circuit attached to the
output, a -180 ? phase-delay occurs in that area. If ESR component is present there, however, a +90 ? phase-lead
occurs to shift the phase delay to -90 ? . Since the phase delay is desired to set within 150 ? , this is a very effective
method but has a demerit to increase the ripple component of the output voltage.
(3) LC resonant circuit
V CC
(4) With ESR provided
V CC
L
C
V O
L
R ESR
V O
C
fr=
1
2 p LC
[Hz]
fr=
1
2 p LC
[Hz]: Resonance point
At this resonance point, a -180 ?
phase-delay occurs.
f ESR =
1
2 p R ESR C
[Hz]: Phase lead
A -90 ? phase-delay occurs.
Fig.29
Fig.30
According to changes in phase characteristics due to the ESR, only one phase lead should be inserted. For this
phase lead, select either of the methods shows below.
(5) Insert feedback resistance in the C.
(6) Insert the R3 in integrator.
V O
C1
C2
V O
R3
C2
R1
R1
R2
A
FB
R2
A
FB
Phase lead: f Z =
1
2 p C1R1
[Hz]
Phase lead: f Z =
1
2 p C2R3
[Hz]
Fig.31
Fig.32
For the purpose of canceling the LC resonance, the frequency to insert the phase lead should be set close to the
LC resonant frequency.
For output capacitors having low ESR, such as ceramic capacitor or OS-CON
Unlike the section above, in order to use capacitors having low ESR (i.e., several tens of mW), two phase-leads
should be inserted so that a -180 ∞ phase-delay due to LC resonance will be observed. Example (7) blow shows a
typical phase compensation procedure.
(7) Phase compensation with secondary phase lead
V O
C1
R3
C2
R1
R2
A
FB
Phase lead: f Z1 =
Phase lead: f Z2 =
1
2 p R1C1
1
2 p R3C2
[Hz]
[Hz]
LC resonant frequency: fr=
1
2 p LC
[Hz]
Fig.33
For the settings of phase lead frequency, insert both of the phase leads close to the LC resonant frequency.
12/16
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