参数资料
| 型号： | BD9328EFJ-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 11/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2A 8HTSOP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.9 V ~ 12.6 V |
| 输入电压： | 4.2 V ~ 18 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 380kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-HTSOP-J |
| 其它名称： | BD9328EFJ-E2DKR |
BD9328EFJ
Technical Note
● Layout Pattern Consideration
Two high pulsing current flowing loops exist in the buck regulator system. The first loop, when FET is ON, starts from the
input capacitors, to the VIN terminal, to the SW terminal, to the inductor, to the output capacitors, and then returns to the
input capacitor through GND. The second loop, when FET is OFF, starts from the low FET, to the inductor, to the output
capacitor, and then returns to the low FET through GND. To reduce the noise and improve the efficiency, please minimize
these two loop area. Especially input capacitor, output capacitor and low FET should be connected to GND plain.
PCB Layout may affect the thermal performance, noise and efficiency greatly. So please take extra care when designing
PCB Layout patterns.
VIN
C IN
FET
L
C OUT
V OUT
Fig.25 Current loop in Buck regulator system
? The thermal Pad on the back side of IC has the great thermal conduction to the chip. So using the GND plain as broad and
wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat to the different layer is
also effective.
? The input capacitors should be connected as close as possible to the VIN terminal.
? Keep sensitive signal traces such as trace connected FB and COMP away from SW pin.
? The inductor and the output capacitors should be placed close to SW pin as much as possible.
C IN
L
BST
VIN
SW
GND
C OUT
SS
EN
COMP
FB
V OUT
Fig.26 The example of PCB layout pattern
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
11/15
2011.02 - Rev.A
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