参数资料
型号: BD9328EFJ-E2
厂商: Rohm Semiconductor
文件页数: 9/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 8HTSOP
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.9 V ~ 12.6 V
输入电压: 4.2 V ~ 18 V
PWM 型: 电流模式
频率 - 开关: 380kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 标准包装
供应商设备封装: 8-HTSOP-J
其它名称: BD9328EFJ-E2DKR
BD9328EFJ
Technical Note
(2) Loop Compensation
Choosing compensation capacitor C CMP and resistor R CMP
The current-mode buck converter has 2-poles and 1-zero system. Choosing the compensation resistor and capacitor is
important for a good load-transient response and good stability.
The example of DC/DC converter application bode plot is shown below.
The compensation resistor R CMP will decides the cross over frequency F CRS (the frequency that the total DC-DC
loop-gain falls to 0dB).
Setting the higher cross over frequency achieves good response speed, however less stability. While setting the lower
cross over frequency shows good stability but worse response speed.
The 1/10 of switching frequency for the cross over frequency shows a good performance at most applications.
( i ) Choosing phase compensation resistor R CMP
The compensation resistor R CMP can be on following formula.
R CMP =
2 π x V OUT x F CRS x C OUT
V FB x G MP x G MA
[ Ω ]
Where
V OUT ; Output voltage, F CRS ; Cross over frequency, C OUT ; Output Capacitor,
V FB ; internal feedback voltage (0.9V (TYP) ), G MP ; Current Sense Gain (7.8A/V (TYP) ) ,
G MA ; Error Amplifier Trans-conductance (300μA/V (TYP) )
Setting V OUT = 3.3V, F CRS = 38kHz, C OUT = 20μF;
R CMP =
2 π x 3.3 x 38k x 20u
0.9 x 7.8 x 300u
=
7.48k ~= 7.5k
[ Ω ]
( ii ) Choosing phase compensation capacitor CCMP
For the stability of DC/DC converter, canceling the phase delay that derives from output capacitor C OUT and
resistive load R OUT by inserting the phase advance.
The phase advance can be added by the zero on compensation resistor R CMP and capacitor C CMP .
Making Fz= F CRS / 6 gives a first-order estimate of C CMP .
Compensation Capacitor
C CMP =
1
2 π x R CMP x Fz
[F]
Setting Fz= F CRS /6 = 6.3kHz;
Compensation Capacitor
C CMP =
1
2 π x 7.5k x 6.3k
=
3.54n ~= 3.3n
[F]
( iii ) The condition of the loop compensation stability
The stability of DC/DC converter is important. To secure the operating stability, please check the loop compensation
has the enough phase-margin. For the condition of loop compensation stability, the phase-delay must be less than
150 degree where Gain is 0 dB.
Feed forward capacitor C RUP boosts phase margin over a limited frequency range and is sometimes used to
improve loop response. C RUP will be more effective if R UP >> R UP ||R DW
V OUT
Gain [dB]
A
(a)
R UP
R DW
C RUP
FB
0.9V
COMP
R CMP
PHASE
0
0
- 90
- 90°
F CRS
GBW(b)
F
Fig.20
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
C CMP
- 180
9/15
PHASE MARGIN
Fig.21
- 180°
F
2011.02 - Rev.A
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