参数资料
| 型号： | BD9775FV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 10/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-SSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 占空比： | 48% |
| 电源电压： | 6 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-LSSOP（0.220"，5.60mm） |
| 包装： | 标准包装 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9775FV-E2DKR |
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(7) Setting over current detection values
The current limit value （ ILimit ） is determined by the resistance of the RCL established between CL and VCCCL.
VCCCL
VIN
I L
Over current detection point
RCL
CL
I L
L
Vo
ILimit =
90m
RCL
[A] ??? (13)
Fig-23
Fig-24
There are 2 current limit function (ON/OFF control type and OFF latch type) toggled by LOFF pin.
? LOFF=L (0<LOFF<1V): Off Latch Type Current Limit
The output becomes OFF and latched when SS=H and, current limit operation, and the output voltage is less than or equal
to 70% of Vo. The OFF latch is deactivated by re-inputting EN signal or VCC control input (switch OFF and ON once more).
? LOFF=H (1<LOFF<VREG5): ON/OFF Control Type Current Limit
When the current goes beyond the threshold value, the current can be limited by reducing the ON Duty Cycle. When the load
goes back to the normal operation, the output voltage also becomes back on to the specific level.
Vo
LOFF=L
（ OFF Latch ）
Fig-25
The current limit value
Vo × 70%
LOFF=H
Io
(8) Method for determining phase compensation
Conditions for application stability
Feedback stability conditions are as follows:
? When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°):
a dual-output high-frequency step-down switching regulator is required
Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no
more than 1/10 the switching frequency. In summary, target characteristics for application stability are:
? Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB)
? GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency.
Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response.
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the
application.
GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger
capacitor will serve to lower GBW if desired.
①
General use integrator (low-pass filter)
②
Integrator open loop characteristics
A
Phase 0
[deg] -90 0
-20dB/decade
2 π RCA
2 π RC
Feedback
R
FB
A
C
COMP
Gain
[dB] 90
18 0
0
0
-9
(a)
-90 °
GBW(b)
Phase margin -180 °
1
point (a) fa = 1.25[Hz]
point (b) fa = GBW [Hz]
1
-180 0
-18
Fig-26
Fig-27
The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus serves
as the system’s low-pass filter.
In DC/DC converter applications, R is established parallel to the feedback resistance.
10/29
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