参数资料
| 型号： | BD9775FV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 27/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-SSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 占空比： | 48% |
| 电源电压： | 6 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-LSSOP（0.220"，5.60mm） |
| 包装： | 标准包装 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9775FV-E2DKR |
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9) Applications with modes that reverse VCC and pin potentials may cause
damage to internal IC circuits.
For example, such damage might occur when VCC is shorted with the
GND pin while an external capacitor is charged.
It is recommended to insert a diode for preventing back current flow
in series with VCC or bypass diodes between VCC and each pin.
Countercurrent
prevention diode
Vcc
Pin
Bypass diode
Fig.9
10) Timing resistor and capacitor
Timing resistor(capacitor) connected between RT(CT) and GND, has to be placed near RT(CT) terminal 3pin(4pin). And pattern has to be short
enough.
VREF
VCC
11) The Dead time input voltage has to be set more than 1.1V.
Also, the resistance between DTC and VREF is used more than 30k ? to work OCP function reliably.
12) The energy on DTC1 （ 8pin ） and DTC2 （ 9pin ） is discharged when CTL1 （ 12pin ） and CTL2 （ 13pin ） are OFF, respectively, or VCC （ 14pin ）
is OFF (UVLO activation). However, it is considerable to occur overshoot when CTL and VCC are turned on with remaining more than 1V on
the DTC.
tsw
13) If Gate capacitance of P-channel MOSFET or resistance placed on
Gate is large, and the time from beginning of Gate switching to the end of Drain’s (tsw),
is long, it may not start up due to the OCP malfunction.
To avoid it, select MOSFET or adjust resistance as tsw becomes less than 270nsec.
GATE
DRAIN
Fig.10
14) IC pin input
This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety
of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart,
○ the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
○ Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent
elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an
inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit
operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is
not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower
than the GND (PCB) voltage to input and output pins.
Resistor
Transistor （ NPN ）
(PINA)
(PINB)
C
B
E
(PINB)
(PINA)
P
+
P
P
+
P
+
P
P
+
B
C
N
P
N
Parasitic element
GND
N
N
P substrate
GND
N
E
GND
Parasitic element
pd(W)
1.0
Parasitic element or transistor
Fig.11
Parasitic element or transistor
0.8
0.6
②
0.85W
0.4
0.2
①
0.64W
① 0.587W
① With no heat sink
② Copper laminate area 70 mm×70mm
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE
：
Ta( ℃)
Fig.12
27/29
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| BD9778F | 制造商:ROHM 制造商全称:Rohm 功能描述:Flexible Step-Down Switching Regulator |
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