参数资料
| 型号： | BD9775FV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-SSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 占空比： | 48% |
| 电源电压： | 6 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-LSSOP（0.220"，5.60mm） |
| 包装： | 标准包装 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9775FV-E2DKR |
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When electrolytic or other high-ESR output capacitors are used:
Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several
Ω ). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these
locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to -90°
in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous
approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components.
③ LC resonance circuit
Vcc
Vo
④ ESR connected
V c c
Vo
L
C
Fig-28
L
C
R ESR
Fig-29
fr =
1
2 π√ LC
[Hz]
fr =
resonance point1
2 π√ LC
[Hz] ： Resonance Point
2 π R ESR C
Resonance point phase margin -180 °
1
f ESR = [Hz] :Zero
-90 ° :Pole
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose
one of the following methods to add the phase lead.
⑤
Add C to feedback resistor
Vo
⑥
Vo
Add R3 to aggregator
R1
C1
FB
C2
R1
FB
R3
C2
R2
Fig-30
A
COMP
R2
A
Fig-31
COMP
Phase lead fz =
1
2 π C1R1
[Hz]
Phase lead fz =
1
2 π C2R3
[Hz]
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.
When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:
Where low-ESR (on the order of tens of m Ω ) output capacitors are employed, a two phase-lead insertion scheme is
required, but this is different from the approach described in figure ③ ~ ⑥ , since in this case the LC resonance gives rise
to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can be
implemented.
⑦
Phase compensation provided by secondary (dual) phase lead
Vo
R1
C1
R3
C2
Phase lead fz1 =
1
2 π R1C1
[Hz]
R2
FB
A
COMP
1
Phase lead fz2 = [Hz]
2 π R3C2
1
LC resonance frequency fr =
2 π√ LC
[Hz]
Fig-32
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.
This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount
of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect
the DCDC characteristics. Please verify and confirm using practical applications.
11/29
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