参数资料
| 型号： | BD9853AFV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 9/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 2MHz |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9853AFV-E2DKR |
BD9853AFV
● Application component selection and settings
Determining output voltage
Output voltage is determined by dividing the resistance of the
external resistors.
VOUT ＝ 0.8V×(1 + R2/R1)
R2
Technical Note
V OUT
INV
⑦ ⑩
R1
determining the oscillation frequency
The oscillation pin is set by the resistor connected to the RT terminal (5 PIN).
10.000
1.000
0.100
0.010
0.001
RT
⑤
R RT
1
10
100
1000
Phigh=Iout ×RDS(ON)×VOUT/VIN (PMOS conduction loss)
Plow=Iout ×RDS(ON)×(1-VOUT/VIN) (NMOS conduction loss)
T iming Res is t a nce(k Ω)
Selecting the external MOSFET
In the BD9853AFV design, the main side (OUT1H, OUT2H) is provided with an external PCH FET, while an NCH FET is
used on the synchronous rectification side (OUT1L, OUT 2L) .
FET selection should be made in conformance with the following relative configurations for maximum drain voltage (VDSS),
maximum gate source voltage (VGS), maximum output current, on-resistance RDS (ON) and gate capacitance (Ciss) loss:
? Maximum drain voltage (VDSS) is higher than the IC’s maximum input voltage (VIN).
? Maximum gate source voltage is higher than the IC gate driving voltage (REGA, VCC-REGB).
? Maximum output current is higher than the combined maximum load current and coil ripple current ( ⊿ I L ).
? The sum of on-resistance RDS (ON) and gate capacitance (Ciss) conduction loss, together with the switching loss,
must not exceed the power dissipation (pd) for the package.
FET conduction loss Phigh and Plow are defined as follows:
2
2
Iout ： output load current, RDS(ON) : FET ON resistance value, VIN : input voltage, Vout : output voltage
FET switching loss PSW is calculated as follows:
PSW=VIN/2×(tr + tf)×fosc×Iout
VIN : input voltage, tr : drain waveform rise time, tf : drain waveform fall time, fosc : oscillation frequency, lout : load current
In addition to the criteria for selecting individual MOSFET components, consideration must also be given to the
combination of the PMOS (main side) and NMOS (synchronous side) to be used. The configuration must not generate
any through current with PMOS and NMOS both ON at the same time. In order to meet this condition, the following
formula must be satisfied, where PCH, NCH MOSFET turn-on delay time is represented as tdON, MOSFET turn-off delay
time is tdOFF, and dead time is tdt.
tdt > tdON - tdOFF
The tdt turn-on is (OUTH,OUTL ： H → L)70ns typ. Turn-off is OUTH,OUTL ： L → H)70ns typ. Be sure to confirm that the
process delay time does not pose problem in terms of the overall MOSFET delay.
The following MOSFETs meet all of the selection criteria outlined above, and are recommended for use. Both are
manufactured by ROHM.
PCH: RSS040PO3 NCH: RSS065P03
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
9/16
2009.05 - Rev.A
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