参数资料
| 型号： | BR24L16-W |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 10/41页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 16KBIT 400KHZ 8DIP |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 16K (2K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
| 产品目录页面： | 1379 (CN2011-ZH PDF) |
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BR24L □□ -W Series,BR24S □□□ -W Series
Technical Note
● Write Command
○ Write cycle
? Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
S
W
T
A
R
I
S
T
R
T
SLAVE
ADDRESS
T
E
WORD
ADDRESS
DATA
O
P
SDA
*1 As for WA7, BR24L01A-W becomes Don’t care.
LINE
1 0 1 0 A2 A1 A0
Note)
WA
7
R A *1
/ C
WA
0
A
C
D7
D0
A
C
W K
K
K
Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W)
S
W
T
A
R
I
S
T
R
T
SLAVE
ADDRESS
T
E
1st WORD
ADDRESS
2nd WORD
ADDRESS
DATA
O
P
SDA
LINE
1 0 1 0 A2 A1 A0
*
*
*
WA WA
12 11
WA
0
D7
D0
*1 As for WA12, BR24L32-W becomes Don’t care.
Note)
R A
/ C
W K
*1
A
C
K
A
C
K
A
C
K
Fig.37 Byte write cycle (BR24L32/64-W)
S
W
T
A
R
I
S
T
SDA
L IN E
R
T
SLAVE
ADDRESS
1 0 1 0 A 2 A 1 A 0
T
E
WA
7
W ORD
A D D R E S S (n )
WA
0
D7
D A TA (n )
D0
*2
D A TA (n +1 5 )
D0
O
P
*1 As for WA7, BR24L01A-W becomes Don’t care.
*2 As for BR24L01A/02-W becomes (n+7).
R A
A
A
A
N o te )
/ C *1
W K
C
K
C
K
C
K
Fig.38 Page write cycle (BR24L01A/02/04/08/16-W)
S
W
T
A
R
I
S
T
R
T
SLAVE
ADDRESS
T
E
1 st W O R D
A D D R E S S (n )
2nd W ORD
A D D R E S S (n )
D A T A (n )
D A TA (n + 3 1 )
O
P
SDA
L IN E
1 0 1 0 A 2 A 1 A 0
*
*
*
WA WA
1 2 11
WA
0
D7
D0
D0
*1 As for WA12, BR24L32-W becomes Don’t care.
N ote )
R A
/ C
W K
*1
A
C
K
A
C
K
A
C
K
A
C
K
Fig.39 Page write cycle (BR24L32/64-W)
? Data is written to the address designated by word address (n-th address)
? By issuing stop bit after 8bit data input, write to memory cell inside starts.
? When internal write is started, command is not accepted for tWR (5ms at maximum).
? By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24L01A-W, BR24L02-W)
: Up to 16bytes (BR24L04-W, BR24L08-W,BR24L16-W)
: Up to 32bytes (BR24L32-W, BR24L64-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P9/32.)
? As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of
word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W,
after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the
address of insignificant 4 bits (insignificant 3 bit in BR24L01A-W, and BR24L02-W) is incremented internally, and data
up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written.
? As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word
address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
*1 In BR24L16-W, A2 becomes P2.
*1 *2 *3
1 0 1 0 A 2 A 1 A 0
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
Fig.40 Difference of slave address of each type
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? 2009 ROHM Co., Ltd. All rights reserved.
10/40
2009.09 - Rev.D
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