参数资料
| 型号： | BR93L46FJ-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 30/41页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1KBIT 2MHZ 8SOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1K (64 x 16) |
| 速度： | 2MHz |
| 接口： | Microwire 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOP-J |
| 包装： | 标准包装 |
| 产品目录页面： | 1380 (CN2011-ZH PDF) |
| 其它名称： | BR93L46FJ-WE2DKR |
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BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
4) Write enable (WEN) / disable (WDS) cycle
～ ～
CS
Technical Note
SK
1
2
3
4
5
6
7
8
～ ～
n
BR93H56/66-WC : n=11
ENABLE=1 1
DISABLE=0 0
～ ～
BR93H76/86-WC : n=13
DI
1
0
0
～ ～
DO
High-Z
Fig. 33 Write enable (WEN) / disable (WDS) cycle
At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
disable command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
○ When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
cancelled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
● Application
1) Method to cancel each command
○ READ
Start bit
1bit
Ope code
2bit
Address
8bit
*1
Data
16bit
*1 Address is 8 bits in BR93H56-WC, and BR93H66-WC.
Address is 10 bits in BR93H76-WC, and BR93H86-WC.
Cancel is available in all areas in read mode.
● Method to cancel ： cancel by CS= “ L ”
Fig.34 READ cancel available timing
○ WRITE, WRAL
? Rise of 27clock
*2
SK
DI
26
D1
a
27
D0
b
28
c
29
Enlarged figure
Start bit
1bit
Ope code
2bit
Address
8bit
*1
Data
16bit
tE/W
a
b
C
a ： From start bit to 27 clock rise
Cancel by CS=“L”
b ： 27 clock rise and after * 2
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c ： 28 clock rise and after * 3
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
*1 Address is 8 bits in BR93H56/66-WC
Address is 10 bits in BR93H76/86-WC
*2 27 clocks in BR93H56/66-WC
29 clocks in BR93H76/86-WC
*3 28 clocks in BR93H56/66-WC
30 clocks in BR93H76/86-WC
Note 1) If Vcc is made OFF in this area,
designated address data is not guaranteed,
therefore write once again.
And when SK clock is input continuously, cancellation is not available.
Note 2) If CS is started at the same timing as that of
the SK rise, write execution/cancel becomes
Fig.35 WRITE, WRAL cancel available timing
unstable, therefore, it is recommended to fail in
SK=”L” area. As for SK rise, recommend timing of
tCSS/tCSH or higher.
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
30/40
2011.09 - Rev.G
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BR93L46F-LE2 | 制造商:ROHM 制造商全称:Rohm 功能描述:High Reliability Serial EEPROMs High Reliability Series |
| BR93L46FV | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| BR93L46FVT-W | 制造商:ROHM 制造商全称:Rohm 功能描述:Microwire BUS 1Kbit(64 x 16bit) EEPROM |
| BR93L46FVT-WE2 | 功能描述:电可擦除可编程只读存储器 MICROWIRE BUS 1Kbit 1.8-5.5V Supply RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| BR93L46FV-W | 制造商:ROHM Semiconductor 功能描述:EEPROM,1kb,64Wx16b,Microwire Bus,SSOP8 |
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