参数资料
型号: BR93L46FJ-WE2
厂商: Rohm Semiconductor
文件页数: 33/41页
文件大小: 0K
描述: IC EEPROM 1KBIT 2MHZ 8SOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (64 x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOP-J
包装: 标准包装
产品目录页面: 1380 (CN2011-ZH PDF)
其它名称: BR93L46FJ-WE2DKR
BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
○ READY / BUSY status display (DO terminal)
(common to BR93H56-WC, BR93H66-WC, BR93H76-WC, BR93H86-WC)
This display outputs the internal status signal. When CS is started after tCS (Min.200ns)
from CS fall after write command input, “H” or “L” output.
R/B display = “L” (BUSY) = write under execution
Technical Note
( DO status )
After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically.
And write to the memory cell is made in the period of tE/W, and during this period, other command is not
accepted.
R/B display = “H” (READY) = command wait status
( DO status )
Even after tE/W (max.10ms) (Max.5ms:BR93H66RFVM-WC) from write of the memory cell, the following
command is accepted.
Therefore, CS=“H” in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore,
DI=“L” in the area
CS=“H”. (Especially, in the case of shared input port, attention is required.)
*Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted.
Therefore, status READY output is cancelled, and malfunction and mistake write may be made.
CS
SK
DI
CLOCK
WRITE
INSTRUCTION
STATUS
DO
High-Z
t SV
READY
BUSY
Fig.45 R/B status output timing chart
4) When to directly connect DI and DO
This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart,
meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line.
Microcontroller
EEPROM
DI/O PORT
DI
R
DO
Fig.46 DI, DO control line common connection
○ Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input.
Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the
same time in the following points.
4-1) 1 clock cycle to take in A0 address data at read command
Dummy bit “0” is output to DO terminal.
→ When address data A0 = “1” input, through current route occurs.
EEPROM CS input
EEPROM SK input
“H”
EEPROM DI input
A1
A0
Collision of DI input and DO output
EEPROM DO output
Microcontroller DI/O port
High-Z
A1
A0
0
D15 D14 D13
High-Z
Microcontroller output
Microcontroller input
Fig.47 Collision timing at read data output at DI, DO direct connection
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
33/40
2011.09 - Rev.G
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