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| 型号： | BT864AKPF |
| 英文描述： | Color Encoder Circuit |
| 中文描述： | 颜色编码器电路 |
| 文件页数： | 15/76页 |
| 文件大小： | 1050K |
| 代理商： | BT864AKPF |
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Bt864A/865A
1.0 Circuit Description
YCrCb to NTSC/PAL Digital Video Encoder
1.2 Clock Timing
100138B
Conexant
1-5
1.2 Clock Timing
A clock signal with a frequency twice the pixel sampling rate must be present at
the CLK pin. The device generates an internal pixel CLOCK that in slave mode is
synchronized to the HSYNC* pin. This signal is used to increment the horizontal
pixel and vertical line counters and to register the pixel (P[7:0], Y[7:0], TTXDAT,
RESET*, BLANK*, SLAVE, HSYNC*, and VSYNC*) inputs. All setup and
hold timing specifications are measured with respect to the rising edge of CLK.
1.3 Pixel Input Timing
1.3.1 8-bit YCrCb Input Mode
The 8-bit YCrCb multiplexed input mode is selected by default. Multiplexed Y,
Cb, and Cr data is input through the P[7:0] inputs. By default, the input sequence
for active video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc. in
accordance with CCIR656.
1.3.2 16-bit YCrCb Input Mode
The 16-bit mode is selected by setting the YC16 register bit. Y data is input
through the Y[7:0] inputs. Multiplexed Cb and Cr data is input through the P[7:0]
inputs.
1.3.3 Pixel Synchronization
The default input pixel sequence is such that the next clock after HSYNC* goes
low will be the start of the 4-byte Cb/Y/Cr/Y sequence in 8-bit mode, or Y/Cb
sample pair in 16-bit mode. This is true for slave mode, and for master mode with
the default HSYNC* timing. This sequence can be changed by the SYNCDLY
and CBSWAP bits in both master and slave modes, or by using the variable
HSYNC* timing in master mode.
The SYNCDLY bit will decrease the delay between the HSYNC* pin and the
analog output by one clock cycle. The pixel-to-analog out timing is unaffected.
This makes the next pixel after the falling edge of HSYNC* the last Y of the
Cb/Y/Cr/Y sequence in 8-bit mode.
The CBSWAP bit will shift the sequence at the input such that the next sample
after the falling edge of HSYNC* will be the Cr sample of the Cb/Y/Cr/Y
sequence in 8-bit mode, or the Y/Cr sample pair in 16-bit mode. The relationship
between the HSYNC* pin and the analog output is unaffected, as is the
pixel-to-analog out timing.
相关PDF资料 |
PDF描述 |
|---|---|
| BT865AKPF | Color Encoder Circuit |
| BT867KPF | Color Encoder Circuit |
| BT867KPJ | Color Encoder Circuit |
| BT8920EPJ | Analog-to-Digital Converter， 16-Bit |
| BT8920EPJ600 | Analog-to-Digital Converter， 16-Bit |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BT864AKRF | 制造商:CONEXANT 制造商全称:CONEXANT 功能描述:YCrCb to NTSC/PAL Digital Video Encoder |
| BT864KPF | 制造商:BT 功能描述:COLOR SIGNAL ENCODER, PQFP52 |
| BT864KPF-ES1 | 制造商:BT 功能描述:864KPF-ES1 |
| BT865A | 制造商:CONEXANT 制造商全称:CONEXANT 功能描述:High Performance YCrCb to NTSC/PAL Digital Video Encoders |
| BT865AKPF | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Color Encoder Circuit |
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