参数资料
型号: BT864AKPF
英文描述: Color Encoder Circuit
中文描述: 颜色编码器电路
文件页数: 17/76页
文件大小: 1050K
代理商: BT864AKPF
Bt864A/865A
1.0 Circuit Description
YCrCb to NTSC/PAL Digital Video Encoder
1.4 HSYNC* Timing
100138B
Conexant
1-7
1.4.2 Slave Mode
Slave mode does not support a variable HSYNC* timing mode. The default
pipeline delay from the HSYNC* falling edge to analog sync out falling edge is
47 clocks if SYNCDLY = 0, and 46 clocks if SYNCDLY = 1. The default delay
from the falling edge of HSYNC* input to internal horizontal pixel counter reset
is 5 clocks. In both master and slave modes, the pixel data pipeline delay is 52
clocks.
Figure 1-3. HSYNC* Timing In Master Mode
NOTE(S):
(1)
One clock delay (1/2 pixel) of HSYNC* falling edge, using register SYNCDLY.
(2)
Falling edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCF.
(3)
Rising edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCR.
(4)
Maximum horizontal resolution (see
Table 1-2
).
5. Waveforms not to scale.
Internal Pixel
Clock/Counter
Internal
Horizontal Reset
HSYNC*
(1)
(1)
Active
Video
Color
Burst
Analog Output
Video Waveform
Default
(2)
Default
(3)
Horizontal Sync
Pipeline Delay
Reset
Pixel Count
1
2
3 . . .
(4)
Pixel Count
1
2
3 . . .
(4)
(2)
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