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参数资料
| 型号： | BU-64703B3-190 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 22/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B3-190 |
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29
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
SIMPLE SYSTEM INTERFACE
FIGURE 17 illustrates the capability of the SSRT Mark3 to inter-
face to a system with no host processor in burst mode. In this
example, only one set of external latches is needed to buffer the
data words written by the SSRT Mark3 to the external system. In
burst mode, all received data words are stored in the internal
FIFO until the last word is received. At this point, the SSRT
FIGURE 17. SSRT Mark3-TO-SIMPLE SYSTEM INTERFACE
(SHOWN FOR BURST MODE AND +3.3V TRANSCEIVERS)
D15-D0
Write
Address
Decoder
Read
Address
Decoder
LATCH
TRI-STATE
BUFFER
TRI-STATE
BUFFER
EN
TRI-STATE
BUFFER
EN
L-BRO, T/R, SA4-0,
WC/CWC4-0
MEMWR
DISCRETE
DIGITAL
INPUTS
DISCRETE
DIGITAL
OUTPUTS
AUTO-
CONFIGURATION
(OPTIONAL)
RTACTIVE
DTACK
AUTO_CFG
MEMOE
BU-64703
SSRT Mark3
EN
Clock
Oscillator
CLK-IN
RTAD4-0, RTADP
MSTCLR
+3.3V
RT
ADDRESS
BUS A
DTGRT
+V
10F
.01F
+
3.3V
BUS B
10F
.01F
+
3.3V
+3.3V
Mark3 will transfer the entire contents of the FIFO to the system
if the message is validated. In this case, GBR will be driven low
for two clock cycles following the burst transfer cycle.
If the received message is not valid, the FIFO data will not be
transferred to the external system and GBR will remain high.
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