- 您现在的位置：买卖IC网 > PDF目录256008 > BU-64703B3-190 (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 PDF资料下载
参数资料
| 型号： | BU-64703B3-190 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 44/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B3-190 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页
5
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
The SSRT Mark3 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples
incoming data on both edges of the clock input. This oversam-
pling, in effect, provides for a sampling rate of twice the input
clocks' frequency. Benefits of the higher sampling rate include a
wider tolerance for zero-crossing distortion and improved bit
error rate performance.
The SSRT Mark3 includes a hardwired RT address input. This
includes 5 address lines, an address parity input, and an
address parity error output. The RT address can also be latched
by means of a latching input signal.
The SSRT Mark3 supports command illegalization. Commands
may be illegalized by asserting the input signal ILLEGAL active
low within approximately 2 s after the mid-parity bit zero-cross-
ing of the received command word. Command words may be ille-
galized as a function of broadcast, T/R bit, subaddress, word
count, and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The SSRT Mark3 provides a number of real-time output signals.
These various signals provide indications of message in
progress, valid received message, message error, handshake
fail, loop-test fail or transmitter timeout.
The SSRT Mark3 includes standard DMA handshake sig-
nals (Request, Grant, and Acknowledge) as well as trans-
fer control outputs (MEMOE and MEMWR). The DMA inter-
face operates in a 16-bit mode, supporting word-wide
transfers.
The SSRT Mark3's system interface allows the SSRT Mark3 to
be interfaced directly to a simple system that doesn't include a
microprocessor. This provides a low-cost 1553 interface for A/D
and D/A converters, switch closures, actuators, and other dis-
crete I/O signals.
The SSRT Mark3 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the SSRT Mark3 to
transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a rate
of one data word every three clock cycles. Burst mode negotiates
only once for use of the subsystem bus. Negotiation is performed
only after all 1553 data words have been received and validated. In
non-burst mode, the SSRT Mark3 will negotiate for the local bus
after every received data word. The data word transfer period is
three clock cycles for each received 1553 data word.
The SSRT Mark3 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a small amount
of "glue" logic, the SSRT Mark3 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a
INTRODUCTION
GENERAL
The BU-64703 Simple System RT Mark3 (SSRT Mark3) is a
complete MIL-STD-1553 Remote Terminal (RT) bus interface
unit. Contained in this hybrid are a dual transceiver and
Manchester II encoder/decoder, and MIL-STD-1553 Remote
Terminal (RT) protocol logic. Also included are built-in self-test
capability and a parallel subsystem interface. The subsystem
interface includes a 12-bit address bus and a 16-bit data bus that
operates in a 16-bit DMA handshake transfer configuration. The
local bus and associated control signals are optimized for +3.3
volt logic but are +5 volt tolerant.
The transceiver front end of the SSRT Mark3 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +3.3V voltage source (+5.0V available).
The voltage source transmitters provide superior line driving
capability for long cables and heavy amounts of bus loading. In
addition, the monolithic transceivers can provide a minimum stub
voltage level of 20 volts peak-to-peak transformer coupled, mak-
ing the SSRT Mark3 suitable for MIL-STD-1760 applications. To
provide compatibility to McAir specs, the SSRT Mark3 is avail-
able with an option for transmitters with increased rise and fall
times.
Besides eliminating the demand for an additional power supply,
the use of a +3.3V only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of a higher terminal input impedance than is possible
for a 15V, 12V or 5V transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553 val-
idation test. This allows for longer cable lengths between a sys-
tem connector and the isolation transformers of an embedded
1553 terminal.
The receiver sections of the SSRT Mark3 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The SSRT Mark3 implements all MIL-STD-1553 message for-
mats, including all 13 MIL-STD-1553 dual redundant mode
codes. Any subset of the possible 1553 commands (broadcast,
T/R bit, subaddress, word count/mode code) may be optionally
illegalized by means of an external PROM, PLD, or RAM. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined command word and correct word count. If the SSRT
Mark3 is the receiving RT in an RT-to-RT transfer, it verifies that
the T/R bit of the transmit command word is logic "1" and that the
transmitting RT responds in time and contains the correct RT
address in its Status Word.
相关PDF资料 |
PDF描述 |
|---|---|
| BU-61580G0-150W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G0-180K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G1-150S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G2-110Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G3-142Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-65-0 | 功能描述:测试电夹 ALLIGATOR CLIP BLK RoHS:否 制造商:Pomona Electronics 类型:Minigrabber clip 颜色:Black |
| BU65-0 | 制造商:MUELLER ELECTRIC CO. 功能描述: 制造商:Mueller Electric Company 功能描述: |
| BU-651-0 | 功能描述:测试电夹 Black Shrouded Small RoHS:否 制造商:Pomona Electronics 类型:Minigrabber clip 颜色:Black |
| BU-651-2 | 功能描述:测试电夹 Red Shrouded Small A RoHS:否 制造商:Pomona Electronics 类型:Minigrabber clip 颜色:Black |
| BU65170G0-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Interface IC |
发布紧急采购，3分钟左右您将得到回复。