- 您现在的位置：买卖IC网 > PDF目录223464 > BU-64703B4-300 (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 PDF资料下载
参数资料
| 型号： | BU-64703B4-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 33/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B4-300 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
39
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
SIGNAL
TABLE 11. DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS
PIN
DTACK (O)
MEMWR (O)
MEMOE (O)
HS_FAIL (O)
DTGRT (I)
35
28
20
63
72
DESCRIPTION
Data Transfer Acknowledge. Active low output signal used to indicate the SSRT Mark3’s acceptance of the system data
bus (D15-D0), in response to a data transfer grant (DTGRT). The SSRT Mark3's data transfers over D15-D0 will be
framed by the time that DTACK is asserted low.
If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of MSTCLR,
following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted low to enable configu-
ration data to be read from an external tri-state buffer.
For transmit messages, or receive messages in non-burst mode, or for receive messages to subaddress 30 assuming
that Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of individual words
between the external system and the SSRT Mark3.
For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the DTREQ-
to-DTGRT handshake following the receipt of the last received data word. It will remain low for the duration of the DMA
burst write transfer from the SSRT Mark3 to the external system. The total time for a burst write transfer is three clock
cycles times the number of data words.
Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT Mark3 write cycles.
Used to transfer data from the SSRT Mark3 to the external system. The external system may latch data on either the
falling or rising edge of MEMWR.
Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external system to be
enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the external system. The
SSRT Mark3 latches the data one clock cycle prior to the rising edge of MEMOE.
Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system did not
respond with a DTGRT in time, following the SSRT Mark3's assertion of DTREQ.
Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT Mark3 assert-
ing DTREQ low in order to enable the SSRT Mark3 to read data from or write data to the external subsystem.
The maximum allowable time from DTREQ to DTGRT is 10 s.
If the SSRT Mark3's DMA handshake isn't required, DTGRT may be hardwired to logic "0".
Data Transfer Request. Active low level output signal used to request use of the external system data bus (D15-D0).
DTREQ (O)
29
DESCRIPTION
Remote Terminal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and RTADP
input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity.
Note, if RT_AD_ERR is low, then the SSRT Mark3 will not recognize any valid Command Word received to its own RT
address.
RT_AD_ERR (O)
6
RT Address inputs.
RTAD0 (I) (LSB)
RTAD1 (I)
RTAD2 (I)
RTAD3 (I)
RTAD4 (I) (MSB)
38
45
24
39
40
SIGNAL
TABLE 12. RT ADDRESS
Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT
to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD4-RTAD0
and RTADP.
RTADP (I)
44
PIN
RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT Mark3 is configured to accept a hardwired RT
address from RTAD4-RTAD0 and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP
will be latched internally by the SSRT Mark3 on the rising edge of RT_AD_LAT.
RT_AD_LAT (I)
36
相关PDF资料 |
PDF描述 |
|---|---|
| BU-64703B9-300 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| BU-65551M2-300 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, XMA68 |
| BU-65550M1-300 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, XMA68 |
| BU-66318G0-110 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| BU2294AF | 67.735842 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-65-0 | 功能描述:测试电夹 ALLIGATOR CLIP BLK RoHS:否 制造商:Pomona Electronics 类型:Minigrabber clip 颜色:Black |
| BU65-0 | 制造商:MUELLER ELECTRIC CO. 功能描述: 制造商:Mueller Electric Company 功能描述: |
| BU-651-0 | 功能描述:测试电夹 Black Shrouded Small RoHS:否 制造商:Pomona Electronics 类型:Minigrabber clip 颜色:Black |
| BU-651-2 | 功能描述:测试电夹 Red Shrouded Small A RoHS:否 制造商:Pomona Electronics 类型:Minigrabber clip 颜色:Black |
| BU65170G0-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Interface IC |
发布紧急采购，3分钟左右您将得到回复。