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参数资料
| 型号： | BU-64703B4-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 45/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B4-300 |
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6
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
shared RAM for each broadcast / T/R bit / subaddress / mode
code.
BU-64703E8 SSRT MARK3 (+3.3V) TRANSFORMER
EVALUATION BOARD (SEE FIGURE 2)
The BU-64703E8 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of the +3.3V SSRT Mark3. The user will be able to
quickly perform functional tests and run their system software
utilizing this relatively small (2.0” x 2.5”) evaluation board.
The BU-64703E8 consists of a PC board incorporating a +3.3V
SSRT Mark3 (BU-64703G8), necessary decoupling capacitors,
and associated isolation transformers. The MIL-STD-1553 outputs
have been factory configured for Stub (transformer) coupling. The
board supports the signal fan-out of the +3.3V SSRT Mark3 to 96
pins subdivided into (4) dual inline, berg type pin rows. These pins
(0.025” square max) and their row placement adhere to standard
0.100” vector board spacing.
ADDRESS MAPPING
A typical addressing scheme for the SSRT Mark3 12-bit address
bus could be as follows:
A11:
BROADCAST/OWNADDRESS
A10:
TRANSMIT/RECEIVE
A9-A5:
SUBADDRESS 4-0
A4-A0:
WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" allo-
cation scheme for the storage of data words. The 12 address out-
puts may be used to map into 4K words of processor address
space. The SSRT Mark3's addressing scheme maps messages
in terms of broadcast/ownaddress, transmit/receive, subad-
dress, and word/count mode code. A 32-word message block is
allocated for each T/R-subaddress.
For non-mode code messages, the Data Words to be transmit-
ted or received are accessed from (to) relative locations
0 through 31 within the respective message block. For the
MIL-STD-1553B Synchronize with data, Selected transmitter
shutdown, Override selected transmitter shutdown, and Transmit
vector word mode commands which involve a single data word
transfer, the address for the data word is offset from location 0
of the message block for subaddresses 0 and 31 by the value of
the mode code field of the received command word.
The data words transmitted in response to the Transmit last com-
mand or Transmit BIT word mode commands are accessed from
a pair of internal registers.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals
are provided to facilitate communication with the parallel sub-
system. The data bus D15-D0 consists of bi-directional tri-state
signals. The address bus L_BRO, T/R, SA4-SA0, and
WC/MC/CWC4-0; along with the data transfer control signals
MEMOE and MEMWR are two-state output signals.
The control signals include the standard DMA handshake sig-
nals DTREQ, DTGRT, DTACK, as well as the transfer control
outputs MEMOE and MEMWR. HS_FAIL provides an indication
to the subsystem of a handshake failure condition.
Data transfers between the subsystem and the SSRT Mark3 are
performed by means of a DMA handshake, initiated by
the SSRT Mark3. A data read operation is defined to be the trans-
fer of data from the subsystem to the SSRT Mark3. Conversely, a
data write operation transfers data from the SSRT Mark3 to the
subsystem. Data is transferred as a single 16-bit word.
DMA READ OPERATION
In response to a transmit command, the SSRT Mark3 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT Mark3 asserts the signal DTREQ
low. Assuming that the subsystem asserts DTGRT in time, the
SSRT Mark3 will then assert the appropriate values of L_BRO
(logic "0"), T/R (high), SA4-0, and MC/CWC4-0; MEMWR high,
along with DTACK low and MEMOE low to enable data to be
read from the subsystem.
After the transfer of each Data Word has been completed, the value
of the address bus outputs CWC4 through CWC0 is incremented.
DMA WRITE OPERATION
In response to a receive command, the SSRT Mark3 will need to
transfer data to the subsystem. There are two options for doing
this, the burst mode and the non-burst mode. In burst mode, all
received data words are transferred from the SSRT Mark3 to the
subsystem in a contiguous burst, only following the reception of
the correct number of valid data words. In the non-burst mode,
single data words are written to the external subsystem immedi-
ately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT Mark3 asserts DTREQ
low. The subsystem must then respond with DTGRT low.
Assuming that DTGRT was asserted in time, the SSRT Mark3
will then assert DTACK low. The SSRT Mark3 will then assert the
appropriate value of L_BRO, T/R, SA4-0, and MC/CWC4-0,
MEMOE high, and MEMWR low. MEMWR will be asserted low
for one clock cycle. The subsystem may then use either the
falling or rising edge of MEMWR to latch the data. Similar to the
DMA read operation, the address outputs CWC4 through CWC0
are incremented after the completion of a DMA write operation.
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