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参数资料
| 型号： | BU-65743F3-210 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 26/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-210 |
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32
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
RT MEMORY MANAGEMENT
The PCI Mini-ACE Mark3/Micro-ACE TE provides a variety of RT
memory management capabilities. As with the ACE and Mini-
ACE (Plus), and Enhanced Mini-ACE the choice of memory
management
scheme
is
fully
programmable
on
a
transmit/receive/broadcast subaddress basis.
In compliance with MIL-STD-1553B Notice 2, received data from
broadcast messages may be optionally separated from non-
broadcast received data. For each transmit, receive or broadcast
subaddress, either a single-message data block, a double
buffered configuration (two alternating Data Word blocks), or a
variable-sized (128 to 8192 words) subaddress circular buffer
may be allocated for data storage. The memory management
scheme for individual subaddresses is designated by means of
the subaddress control word (reference TABLE 56).
For received data, there is also a global circular buffer mode. In
this configuration, the data words received from multiple (or all)
subaddresses are stored in a common circular buffer structure.
Like the subaddress circular buffer, the size of the global circular
buffer is programmable, with a range of 128 to 8192 data words.
In addition to helping ensure data sample consistency, the circu-
lar buffer options provide a means for greatly reducing host
processor overhead for multi-message bulk data transfer appli-
cations.
End-of-message interrupts may be enabled either globally (fol-
lowing all messages), following error messages, on a
transmit/receive/broadcast subaddress or mode code basis, or
when a circular buffer reaches its midpoint (50% boundary) or
lower (100%) boundary. A pair of interrupt status registers allow
the host processor to determine the cause of all interrupts by
means of a single read operation.
SINGLE BUFFERED MODE
The operation of the single buffered RT mode is illustrated in
FIGURE 6. In the single buffered mode, the respective lookup
table entry must be written by the host processor. Received data
words are written to, or transmitted data words are read from the
data word block with starting address referenced by the lookup
table pointer. In the single buffered mode, the current lookup
table pointer is not updated by the PCI Mini-ACE Mark3/Micro-
ACE TE memory management logic. Therefore, if a subsequent
message is received for the same subaddress, the same Data
Word block will be overwritten or overread.
CIRCULAR BUFFER MODE
The operation of the PCI Mini-ACE Mark3/Micro-ACE TE circular
buffer RT memory management mode is illustrated in FIGURE 7.
As in the single buffered and double buffered modes, the indi-
vidual lookup table entries are initially loaded by the host proces-
sor. At the start of each message, the lookup table entry is stored
in the third position of the respective message block descriptor in
the descriptor stack area of RAM. Receive or transmit data
words are transferred to (from) the circular buffer, starting at the
location referenced by the lookup table pointer.
In general, the location after the last data word written or read
(modulo the circular buffer size) during the message is written to
the respective lookup table location during the end-of-message
sequence. By so doing, data for the next message for the respec-
tive transmit, receive(/broadcast), or broadcast subaddress will
be accessed from the next lower contiguous block of locations in
the circular buffer.
DATA
BLOCKS
DATA BLOCK
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
DESCRIPTOR
STACKS
LOOK-UP
TABLE ADDR
LOOK-UP TABLE
(DATA BLOCK ADDR)
15
13
0
CURRENT
AREA B/A
CONFIGURATION
REGISTER
STACK
POINTERS
(See note)
Note: Lookup table is not used for mode commands when enhanced mode codes are enabled.
FIGURE 6. RT SINGLE BUFFERED MODE
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