参数资料
型号: BU-65743F3-210
厂商: DATA DEVICE CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封装: 0.880 INCH, CERAMIC, QFP-80
文件页数: 52/75页
文件大小: 532K
代理商: BU-65743F3-210
56
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
AD31 (I/O)
27
32-Bit PCI Bus Address / Data lines. Address and Data are multiplexed on the same pins. Each bus oper-
ation consists of an address phase followed by one or more data phases.
Address phases are identified when the control signal FRAME# is asserted. Data transfers occur during
those clock cycles in which the control signals IRDY# and TRDY# are both asserted.
AD30 (I/O)
28
AD29 (I/O)
29
AD28 (I/O)
32
AD27 (I/O)
33
TABLE 76. PCI BUS ADDRESS AND DATA SIGNALS
SIGNAL NAME
DESCRIPTION
PIN
V9
T8
R17
P17
U8
BALL
3V
D7
M10
L10
H16
E7
BALL
5V
AD26 (I/O)
34
AD25 (I/O)
35
AD24 (I/O)
36
AD23 (I/O)
39
AD22 (I/O)
40
N17
V8
P18
M18
J15
L11
N9
L18
K17
J16
AD21 (I/O)
41
AD20 (I/O)
42
AD19 (I/O)
43
AD18 (I/O)
44
AD17 (I/O)
45
J18
K16
H18
K18
L18
G18
J17
G17
J18
K18
AD16 (I/O)
46
AD15 (I/O)
59
AD14 (I/O)
60
AD13 (I/O)
61
AD12 (I/O)
62
K17
D16
E18
D17
B15
H17
D15
F16
D16
C15
AD11 (I/O)
63
D18
D17
AD10 (I/O)
64
AD9 (I/O)
65
AD8 (I/O)
67
AD7 (I/O)
68
AD6 (I/O)
71
A15
A14
B14
A12
B11
C14
A14
C13
A12
A11
AD5 (I/O)
72
B6
J7
AD4 (I/O)
73
AD3 (I/O)
74
AD2 (I/O)
75
AD1 (I/O)
76
AD0 (I/O)
(LSB)
77
A11
C12
C10
A10
B10
C10
C6
B7
A9
B10
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