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参数资料
| 型号： | BU-65743F3-210 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 75/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-210 |
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9
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
PCI COMMAND REGISTER
Reserved: These bits are read-only and return zeroes when
read.
SERR# Enable: This is an enable bit for the SERR# driver. A
value of 0b disables the driver. A value of 1b enables the driver.
The value after RST# is 0b.
Parity Error Control: This bit controls the device's response to
parity errors. When the bit is 1b, the device will take its normal
action when a parity error is detected. When this bit is 0b, the
device will ignore any parity errors that it detects and continue
normal operation. The value after RST# is 0b.
Memory Space: This bit controls the device's response to mem-
ory space accesses. A value of 0b disables the device response.
A value of 1b allows the device to respond to memory space
accesses. The value after RST# is 0b.
PCI STATUS REGISTER
This register records status information for PCI bus related
events. Reads to this register behave normally, but writes can
only reset bits. A bit is reset whenever the register is written and
the data in the corresponding bit location is a 1.
Detected Parity Error: This bit will be set by the device when-
ever it detects a parity error, even if the Parity Error Control bit in
the PCI Control register is 0b.
Signaled System Error: This bit indicates when the device has
asserted SERR#. The value after RST# is 0b.
Signaled Target Abort: This bit is set whenever the device ter-
minates a transaction with a Target-Abort. The value after RST#
is 0b.
DEVSEL# Timing: The PCI Mini-ACE Mark3 is 01b, medium.
Fast Back-to-Back Capable: This bit is set to 1b and indicates
that the device is capable of accepting fast back-to-back trans-
actions.
Reserved: These bits are read-only and return zeroes when
read.
Subsystem Vendor ID/Subsystem Device ID field is an alias of
the Vendor ID/Device ID fields in Configuration Register 00h.
Base Address Registers are used to implement ACE memory
space (BAR0) and ACE register space (BAR1). Base Address
Registers 2 through 5 are not used.
BAR0 is used to access ACE memory space. The ACE is allot-
ted a maximum of 64K words, 128K bytes, for its memory space.
BAR0 will read back as FFFE0000 after all Fs are written to it.
0
29:28
SIGNALED SYSTEM ERROR
30
DETECTED PARITY ERROR
31
DESCRIPTION
BIT
TABLE 6. PCI STATUS REGISTER
0
24
DEVSEL# TIMING = 01 (MEDIUM)
26:25
SIGNALED TARGET ABORT
27
0
22:21
FAST BACK-TO-BACK CAPABLE = 1
23
RESERVED, 0’S
20:16
BAR0 will read back the same for both the 4K word ACE parts
(BU-65743/843) and the 64K word ACE (BU-65864).
PCI MINI-ACE MARK3/Micro-ACE TE Memory Space: The least
significant bit (LSB) of the PCI address is dropped to form the
ACE memory address.
BAR1 is used to access ACE register locations. The ACE is allot-
ted a maximum of 4K bytes for its register space. BAR1 will read
back as FFFFF000h after all Fs are written to it. All ACE register
locations are accessible through the PCI host via the BAR1 off-
sets 000h to 0FCh. The PCI-to-ACE interface control/status reg-
isters are at 800h to 81Ch. PCI accesses outside of these spe-
cific regions (e.g., to offset 100h or 820h, etc.) will produce
Target Aborts.
PCI MINI-ACE MARK3/Micro-ACE TE Register Space: Register
accesses are on a 32-bit boundary: the last 2 bits of the PCI
address are dropped to form the internal ACE address. (e.g. 000
= ACE Reg 0, 004 = ACE Reg1, 008 = ACE Reg2, etc.). Refer to
TABLE 18 for a listing of these registers. These registers are
nearly 100% compatible with the Enhanced mini-ACE registers.
For an exhaustive discussion of these registers and 1553
BC/RT/MT operation, please refer to the "Enhanced mini-ACE
User Guide".
PCI MINI-ACE MARK3/MICRO-ACE TE
MEMORY SPACE
00000-1FFFC
DEFINITION
ADDRESS
OFF-SET
TABLE 7. (BAR0) ACE MEMORY
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