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参数资料
| 型号： | BU-65743F3-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 38/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-300 |
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43
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
Table 62 provides the timing parameters for 3.3V PCI signaling
environments applicable to the PCI Mini-ACE Mark3/Micro-ACE
TE, and FIGURE 13 shows the timing reference points. The tim-
ing parameters apply to the other timing diagrams, but are not
illustrated. The PCI Mini-ACE Mark3/Micro-ACE TE conforms to
revision 2.2 of the PCI Local Bus specification. The timing para-
meters are provided here for ease of reference only.
FIGURE 13 illustrates a PCI read from the PCI Mini-ACE
Mark3/Micro-ACE TE's configuration space. The PCI Mini-ACE
Mark3/Micro-ACE TE only responds to Type Zero configuration
access: AD[1:0] must be 00 during the command phase. The PCI
Mini-ACE Mark3/Micro-ACE TE will drive a full Dword on the AD
lines independent of which byte enables are asserted during the
configuration read.
FIGURE 14 illustrates a PCI single write to PCI Mini-ACE
Mark3/Micro-ACE TE configuration space. The PCI Mini-ACE
Mark3/Micro-ACE TE only responds to Type Zero configuration
access: AD[1:0] must be 00 during the command phase. Note
that all combinations of byte enables for configuration writes are
supported. If no byte enables are asserted during a burst write to
configuration space no internal write will occur, but the internal
address will be incremented.
FIGURE 15 shows the specific case of memory reads from the
PCI-ACE interface registers at BAR1 800h-81Ch. Note that
these registers are accessed quickly and without the Delayed
Read Request mechanism required by reads from the other
memory locations (see next section).
FIGURE 16 illustrates the process of reading an ACE memory (BAR0)
or ACE register (BAR1 00-FCh) location.The actual read shown is that
of a single word read, due to the ~600 nS response time shown, see
following text and timing formula tables. If the write FIFO is empty and
there isn't a previous Delayed Read Request (DRR) pending, a read
from these locations enques a DRR, which is then processed by the
PCI Mini-ACE Mark3/Micro-ACE TE. If either of these conditions is true,
the PCI Mini-ACE Mark3/Micro-ACE TE will respond with a Retry, but
will not enque any new DRR.
The PCI Mini-ACE Mark3/Micro-ACE TE responds to the first read with
a Retry. By PCI rules the master must repeat the same exact request
until it completes. This is shown by the master's second read attempt,
which also produces a Retry. Each repeated read request from the
master will be target terminated with a Retry until the data from the
enqued DRR is present in the PCI Mini-ACE Mark3/Micro-ACE TE's
PCI interface. The successful completion is shown at the third read
request, which produces a Disconnect with Data.
This process applies to any memory read from legal address space
other than the PCI-ACE interface registers at BAR1 offset 800-81Ch.
FIGURE 12. PCI SINGLE MEMORY WRITE TO PCI MINI-ACE MARK3/MICRO-ACE TE
1
2
3
4
5
6
7
PCI single write to any legal memory location (C/BE# = 7h)
ADRS
DATA
7h
Byte Enables
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
INPUT HOLD TIME FROM CLK
th
INPUT SETUP TIME TO CLK
tsu
CLK TO SIGNAL VALID DELAY
tv
PARAMETER
SYMBOL
TABLE 62. PCI INTERFACE TIMINGS
0
7
2
MIN
11
MAX
ns
UNITS
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