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参数资料
| 型号： | BU-65743F3-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 42/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-300 |
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47
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
FIGURE 17 illustrates a 16 Dword (32 word) PCI memory write
burst, with the write FIFO empty (or with enough free space to
absorb the 16 Dwords in the FIFO). The write FIFO accepts PCI
memory writes to the ACE memory (BAR0) and ACE registers
(BAR1 offset 00h - FCh). It does not accept writes to the PCI
interface registers at BAR1 offset 800-81Ch. Writes to the BAR1
800-81Ch space go directly into the PCI interface registers. The
32 byte write shown could be an entire 1553 message being writ-
ten to ACE memory.
Writes into the BAR 0 space must be word or Dword. If only one
byte enable is asserted in a word, the PCI Mini-ACE
Mark3/Micro-ACE TE terminates the transaction with a Target-
Abort.
Writes into the BAR 1 00-FCh space must be word or Dword. If
only one byte enable is asserted in a word, the PCI Mini-ACE
Mark3/Micro-ACE TE terminates the transaction with a Target-
Abort. Since the ACE registers in this space are really 16 bit reg-
isters packed into the lower word of a 32bit structure, only lower
word or Dword writes transfer bits into these ACE registers.
In addition, as per PCI spec, a Memory Write and Invalidate
(C/BE[3:0]# = Fh) command will be aliased to the basic Memory
Write command and the timing diagram would look the same as
FIGURE 17.
INTERFACE TO MIL-STD-1553 BUS WITH 3.3V TRANS-
CEIVERS
FIGURE 18 illustrates the interface between the PCI Mini-ACE
Mark3/PCI Micro-ACE TE (with 3.3V transceivers) and a MIL-
STD-1553 bus. Connections for both direct (short stub) and
transformer (long stub) coupling, as well as the peak to peak
voltage levels at various points (when transmitting), are indicat-
ed in the diagram.
The new 3.3V isolation transformers for the PCI Mini-ACE
Mark3/Micro-ACE TE series now contain only one set of output
windings. Different isolation transformers are now required for a
direct or transformer coupled, MIL-STD-1553 Bus implementa-
tion.
The center tap of the primary winding (the side of the transformer
that connects to the device) must be directly connected to the
3.3V plane. Additionally, a 10uF low inductance tantalum capac-
itor and 0.01uF ceramic capacitor must be mounted as close as
possible and with the shortest leads to the center tap of the
transformer(s) and the ground plane.
Furthermore, when the transmitter is transmitting, large currents
will flow from the 3.3V plane, into the transformer center tap, thru
the primaries, into the TX/RX pins and then out thru the trans-
ceiver ground pins into the ground plane. The traces in this path
should be sized accordingly and the connections to the ground
plane should be as short as possible.
FIGURE 17. PCI WRITE BURST TO ACE MEMORY WITH FIFO EMPTY
DAT3
0ns
500ns
1000ns
1
PCICLK
AD
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
DAT2
DAT1
A
DAT4
DAT5
DAT6 DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15 DAT16
1
10
20
30
40
50
9
8
7
6
5
4
3
2
11 1213141516 171819
21 22 23 242526 272829
31 323334 35 3637 38 39
41 42 43444546 474849
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