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参数资料
| 型号： | BX80524P366128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 366 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | 1.950 X 1.950 INCH, HEAT SINK, STAGGERED, PLASTIC, PGA-370 |
| 文件页数： | 10/88页 |
| 文件大小： | 1622K |
| 代理商： | BX80524P366128 |
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Intel Celeron Processor
18
Datasheet
For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to
meet VIH requirements and active-high signals should be connected through a pull-down resistor to
meet VIL requirements. Unused CMOS outputs can be left unconnected. A resistor must be used
when tying bi-directional signals to power or ground. For any signal pulled to either power or
ground, a resistor will allow for system testability.
2.7
Intel Celeron Processor System Bus Signal Groups
To simplify the following discussion, the Intel Celeron processor system bus signals have been
combined into groups by buffer type. All Intel
Celeron processor system bus outputs are
open drain and require a high-level source provided externally by the termination or pull-up
resistor.
AGTL+ input signals have differential input buffers, which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term "AGTL+ Input" refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output"
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
EMI pins (S.E.P. Package only) should be connected to motherboard ground and/or to chassis
ground through zero ohm (0
) resistors. The zero ohm resistors should be placed in close
proximity to the SC242 connector. The path to chassis ground should be short in length and have a
low impedance.
The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5 V. The CMOS,
APIC, and TAP outputs are open drain and should be pulled high to 2.5 V. This ensures not only
correct operation for current Intel Celeron processors, but compatibility for future Intel Celeron
processor products as well.
The groups and the signals contained within each group are shown in Table 2. Refer to Section 7.0
for descriptions of these signals.
Table 2.
Intel Celeron Processor System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#,
CMOS Input4
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD1,
SMI#, SLP#2, STPCLK#
CMOS Output4
FERR#, IERR#, THERMTRIP#3
System Bus Clock
BCLK
APIC Clock
PICCLK
APIC I/O4
PICD[1:0]
TAP Input4
TCK, TDI, TMS, TRST#
TAP Output4
TDO
Power/Other5
BSEL, CPUPRES#7, EDGTRL7, EMI6, PLL[2:1]7, SLOTOCC#6, THERMDP,
THERMDN, VCC
1.5
7, VCC
2.5
7, VCC
L2
5, VCC
5
6, VCC
CMOS
7, VCC
CORE, VCOREDET
7, VID[3:0]7,
VID[4:0]6, VREF[7:0]7, VSS, VTT6
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