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参数资料
| 型号： | BX80524P366128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 366 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | 1.950 X 1.950 INCH, HEAT SINK, STAGGERED, PLASTIC, PGA-370 |
| 文件页数： | 9/88页 |
| 文件大小： | 1622K |
| 代理商： | BX80524P366128 |
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Intel Celeron Processor
Datasheet
17
External logic monitoring the VID signals or the voltage regulator may require the VID pins to be
pulled-up. If this is the case, the VID pins should be pulled up to a TTL-compatible level with
external resistors to the power source of the regulator.
The power source chosen must be guaranteed to be stable whenever the voltage regulator’s supply
is stable. This will prevent the possibility of the processor supply going above the specified VCC
CORE
in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this
can be accomplished by using the input voltage to the converter for the VID line pull-ups. In
addition, the power supply must supply the requested voltage or disable itself.,5
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on motherboard.
3. The Intel
Celeron processor core will be powered off 2.0 V.
4. VID4 applies only to the S.E.P. Package. VID[3:0] applies to both S.E.P. and PPGA packages.
5. For PPGA, only the shaded area applies.
2.6
Intel Celeron Processor System Bus Unused Pins
All RESERVED pins must remain unconnected. Connection of these pins to VCC
CORE, VSS, or to any
other signal (including each other) can result in component malfunction or incompatibility with
the location of each RESERVED pin.
For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level
when the core power supply comes up. For more information, please refer to erratum C26 of the
Intel
Celeron Processor Specification Update (Order Number 243748). Also note that the
TESTHI signal is not available on Intel Celeron processors in the PPGA package.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each
PICD line.
For reliable operation, always connect unused inputs or bi-directional signals to their deasserted
signal level. The pull-up or pull-down resistor value is system dependent and should be chosen
such that the logic-high (VIH) and logic-low (VIL) requirements are met.
For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate
has termination resistors. On the other hand, PPGA does not have AGTL+ termination in its
package and must have any unused AGTL+ inputs terminated through a pull-up resistor.
Table 1.
Voltage Identification Definition 1, 2, 3, 5
Processor Pins
VID4
(S.E.P.P. Only)
VID3
VID2
VID1
VID0
VCC
CORE
0
1
1.90
0
1
0
1.95
0
1
2.003
0
2.05
1
1111
No Core
1
1110
2.1
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