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参数资料
| 型号： | BX80524P366128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 366 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | 1.950 X 1.950 INCH, HEAT SINK, STAGGERED, PLASTIC, PGA-370 |
| 文件页数： | 4/88页 |
| 文件大小： | 1622K |
| 代理商： | BX80524P366128 |
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Intel Celeron Processor
12
Datasheet
2.0
Electrical Specifications
2.1
The Intel Celeron Processor System Bus and VREF
Intel Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology. The Intel Celeron processor system bus specification is similar to the
GTL specification, but has been enhanced to provide larger noise margins and reduced ringing. The
improvements are accomplished by increasing the termination voltage level and controlling the
edge rates. Because this specification is different from the standard GTL specification, it is referred
to as Assisted Gunning Transceiver Logic (AGTL+) in this document.
The Intel
Celeron processor varies from the Pentium Pro processor in its output buffer
implementation. The buffers that drive the system bus signals on the Intel Celeron processor are
actively driven to VCC
CORE for one clock cycle during the low-to-high transition. This improves rise
times and reduces overshoot. These signals should still be considered open-drain and require
termination to a supply that provides the logic-high signal level.
The AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used
by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the
processor core by either the processor substrate (S.E.P. Package) or the motherboard (PPGA
package). Local VREF copies should be generated on the motherboard for all other devices on the
AGTL+ system bus.
Termination is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor may contain termination resistors (S.E.P. Package only) that
provide termination for one end of the Intel Celeron processor system bus. Otherwise, this
termination must exist on the motherboard.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on motherboard flight time as opposed to capacitive deratings. Analog signal
simulation of the Intel Celeron processor system bus, including trace lengths, is highly
recommended when designing a system. See the Pentium II Processor AGTL+ Layout Guidelines
and the Pentium II Processor I/O Buffer Models, Quad Format (Electronic Form) for details.
2.2
Clock Control and Low Power States
Intel Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to
reduce power consumption by stopping the clock to internal sections of the processor, depending
on each particular state. See Figure 1 for a visual representation of the Intel Celeron processor low
power states.
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Pentium II Processor Developer's Manual
(Order Number 243502).
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