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| 型号： | BX80552641T2 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 3200 MHz, MICROPROCESSOR, PBGA775 |
| 封装： | FLIP CHIP, LGA-775 |
| 文件页数： | 27/108页 |
| 文件大小： | 3283K |
| 代理商： | BX80552641T2 |
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Datasheet
27
Electrical Specifications
2.6
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing through low
voltage swings and controlled edge rates. Platforms implement a termination voltage level for
GTL+ signals defined as VTT. Because platforms implement separate power planes for each
processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows
for improved noise tolerance as processor frequency increases. Speed enhancements to data and
address busses have caused signal integrity considerations and platform design methods to become
even more critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard
provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die
termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+
signals.
2.6.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input signals have
differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term
“GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving.
Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when
driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependent upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 2-6 identifies which signals are common clock, source
synchronous, and asynchronous.
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相关代理商/技术参数 |
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| BX80552651T2 | 制造商:Intel 功能描述:P4 651 3.4GHZ LP-BTX 2MB - Boxed Product (Development Kits) |
| BX80552651T2 S L94W | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? 4 Processor 651 65nm 3.4GHz 775-Pin FCLGA6 |
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