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参数资料
| 型号： | BXM80526B600128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495 |
| 封装： | BGA2-495 |
| 文件页数： | 13/74页 |
| 文件大小： | 870K |
| 代理商： | BXM80526B600128 |
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Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
13
The Open-drain output signals have open drain drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and
pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated
or driven to VSS when the processor is in a low-power state depending on the condition of the
floating point unit. Since this signal is a DC current path when it is driven to VSS, Intel
recommends that the software clears or masks any floating-point error condition before putting the
processor into the Deep Sleep state.
3.1.5.3
Other Signals
The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep
state. The APIC clock (PICCLK) must be driven whenever BCLK is driven unless the APIC is
hardware disabled or the processor is in the Sleep state. Otherwise, it is permitted to turn off
PICCLK by holding it at VSS. The system bus clock should be held at VSS when it is stopped in the
Deep Sleep state.
In the Auto Halt and Stop Grant states the APIC bus data signals (PICD[1:0]) may toggle due to
APIC bus messages. These signals are required to be tri-stated and pulled-up when the processor
is in the Quick Start, Sleep, or Deep Sleep states unless the APIC is hardware disabled.
3.2
Power Supply Requirements
3.2.1
Decoupling Recommendations
The amount of bulk decoupling required on the VCC and VCCT planes to meet the voltage tolerance
requirements for the mobile Celeron processor are a strong function of the power supply design.
Contact your Intel Field Sales Representative for tools to help determine how much bulk
decoupling is required. The processor core power plan (VCC) should have eight 0.1-F high
frequency decoupling capacitors placed underneath the die and twenty 0.1-
F mid frequency
decoupling capacitors placed around the die as close to the die as flex solution allows. The system
bus buffer power plane (VCCT) should have twenty 0.1-F high frequency decoupling capacitors
around the die.
3.2.2
Voltage Planes
All VCC and VSS pins/balls must be connected to the appropriate voltage plane. All VCCT and VREF
pins/balls must be connected to the appropriate traces on the system electronics. In addition to the
main VCC, VCCT, and VSS power supply signals, PLL1 and PLL2 provide analog decoupling to the
PLL section. PLL1 and PLL2 should be connected according to Figure 4. Do not connect PLL2
directly to VSS. Appendix A contains the RLC filter specification.
Figure 4. PLL RLC Filter
PLL1
PLL2
V
CCT
V0027-01
L1
C1
R1
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