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| 型号： | BXM80526B600128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495 |
| 封装： | BGA2-495 |
| 文件页数： | 8/74页 |
| 文件大小： | 870K |
| 代理商： | BXM80526B600128 |
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Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
9
2.3
GTL+ Signals
The mobile Celeron processor system bus signals use a variation of the low-voltage swing GTL
signaling technology. The mobile Celeron processor system bus specification is similar to the
Pentium II processor system bus specification, which is a version of GTL with enhanced noise
margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Celeron processor.
The GTL+ system bus of the Celeron processor was designed to support high-speed data transfers
with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are
short. It is possible to change the layout and termination of the system bus to take advantage of the
mobile environment using the same GTL+ I/O buffers. In mobile systems the GTL+ system bus is
terminated at one end only. This termination is provided on the processor core (except for the
RESET# signal). Refer to the Mobile Pentium III Processor GTL+ System Bus Layout Guideline
for details on laying out the GTL+ system bus.
2.4
Mobile Celeron Processor CPUID
After a power-on RESET or when the CPUID version information is loaded, register EAX and
EBX[7:0] contains the values shown in Table 4. After the L2 cache is initialized, the CPUID
cache/TLB descriptors will be the values shown in Table 5.
Table 4. Mobile Celeron Processor CPUID
EAX[31:0]
EBX[7:0]
Reserved [31:14]
Type [13:12] Family [11:8]
Model [7:4] Stepping [3:0]
Brand ID
X0
6
8
X
01
Table 5. Mobile Celeron Processor CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 41H
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