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参数资料
| 型号： | BXM80526B600128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495 |
| 封装： | BGA2-495 |
| 文件页数： | 4/74页 |
| 文件大小： | 870K |
| 代理商： | BXM80526B600128 |
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Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
5
2.2
Power Management
2.2.1
Clock Control Architecture
The mobile Celeron processor clock control architecture (Figure 2) has been optimized for leading
edge deep green desktop and mobile computer designs. The clock control architecture consists of
seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop,
Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock state that can be
controlled through the software execution of the HLT instruction. The Quick Start state provides a
very low power and low exit latency clock state that can be used for hardware controlled “idle”
computer states. The Deep Sleep state provides an extremely low-power state that can be used for
“Power-On-Suspend” computer states, which is an alternative to shutting off the processor’s
power. Compared to the Pentium processor exit latency of 1 msec, the exit latency of the Deep
Sleep state has been reduced to 30
sec in the mobile Celeron processor. The Stop Grant and
Sleep states shown in Figure 2 are intended for use in “Deep Green” desktop and server systems
— not in mobile systems. Performing state transitions not shown in Figure 2 is neither
recommended nor supported.
The Stop Grant and Quick Start clock states are mutually exclusive, i.e., a strapping option on
signal A15# chooses which state is entered when the STPCLK# signal is asserted. The Quick Start
state is enabled by strapping the A15# signal to ground at Reset; otherwise, asserting the
STPCLK# signal puts the processor into the Stop Grant state. The Stop Grant state has a higher
power level than the Quick Start state and is designed for Symmetric Multi-Processing (SMP)
platforms. The Quick Start state has a much lower power level, but it can only be used in
uniprocessor platforms. Table 3 provides clock state characteristics, which are described in detail
in the following sections.
2.2.2
Normal State
The Normal state of the processor is the normal operating mode where the processor’s core clock
is running and the processor is actively executing instructions.
2.2.3
Auto Halt State
This is a low-power mode entered by the processor through the execution of the HLT instruction.
The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is
made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#,
INIT#, RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition
to the Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle will be issued.
Deasserting STPCLK# will cause the processor to return to the Auto Halt state without issuing a
new Halt bus cycle.
The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management
Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel
Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System
Management Mode (SMM).
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