参数资料
型号: C8051F018
厂商: Silicon Laboratories Inc
文件页数: 124/154页
文件大小: 0K
描述: IC 8051 MCU 16K FLASH 64TQFP
标准包装: 160
系列: C8051F018
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 托盘
C8051F018
C8051F019
Figure 9.2. Flash Program Memory Security Bytes
0x3E00
0x807F
0x8000
0x3DF
E
Program Memory
Space
0x0000
0x3DFF
Read Lock Byte
Write/Erase Lock Byte
Software Read Limit
Reserved
Bit
Memory Block
7
6
5
4
3
2
1
0
0x2000 - 0x2FFF
0x3000 - 0x3FFF
0x1000 - 0x1FFF
0x0000 - 0x0FFF
0x7FFF
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
Note: Bits 7-0 must all be set to lock
the block at 0x8000-0x807F
0x3DFD
The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block
containing the security bytes. This allows additional blocks to be protected after the block containing the security
bytes has been locked. However, the only means of removing a lock once set is to erase the entire program memory
space by performing a JTAG erase operation (i.e. cannot be done in user firmware). NOTE: Addressing either
security byte while performing a JTAG erase operation will automatically initiate erasure of the entire
program memory space (except for the reserved area). This erasure can only be performed via JTAG. If a
non-security byte in the 0x3C00-0x3DFF page is addressed during erasure, only that page (including the
security bytes) will be erased.
FLASH Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.)
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Access Limit Register (FLACL)
The content of this register is used as the high byte of the 16-bit software read limit address. The 16-
bit read limit address value is calculated as 0xNN00 where NN is replaced by the contents of this
register. Software running at or above this address is prohibited from using the MOVX or MOVC
instructions to read, write, or erase, locations below this address. Any attempts to read locations
below this limit will return the value 0x00.
The Flash Access Limit security feature (see Figure 9.3) protects proprietary program code and data from being read
by software running on the C8051F018/9 MCUs. This feature provides support for OEMs that wish to program the
MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while
allowing additional code to be programmed in remaining program memory space later.
The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory
space. The first is an upper partition consisting of all the program memory locations at or above the SRL address,
and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but
excluding) the SRL address.
Software in the upper partition can execute code in the lower partition, but is
71
Rev. 1.2
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