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| 型号： | C9706AY |
| 英文描述： | ST92141 - 8/16 BIT MCU FOR 3-PHASE AC MOTOR CONTROL |
| 中文描述： | CPU系统时钟发生器| SSOP封装| 48PIN |塑料 |
| 文件页数： | 8/19页 |
| 文件大小： | 248K |
| 代理商： | C9706AY |
C9706
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
Page 8 of 19
Serial Control Registers
NOTE:
The Pin # column lists the affected pin number where applicable. The @Pup column gives the state of the
control register at power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte , two additional bytes must be sent:
1) “
Command Code
“
byte, and
2) “
Byte Count
” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
Byte2,…) will be valid and acknowledged.
Byte 0: Frequency Control Register
(1 = Enable, 0 = Low)
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Pin Description
Spread Spectrum extension (1= on, 0 = off) see table 4, pg. 10
S2
S1
S0
1 = enable byte 0, bits 6, 5, 4, 2, 1 for frequency selection table 4
S4
S3
See Table 3 below
Byte 1: CPU / SDRAM Clock Register
(1=Enable, 0=Low)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
1
1
Pin#
-
-
-
-
40
-
43,44
46
Pin Description
SBW2 (See SST Page 6, Table 3)
SBW1 (See SST Page 6, Table 3)
SBW0 (See SST Page 6, Table 3)
Reserved
SDRAM12
Reserved
CPU,CPU# (0 = disabled, CPU in low and CPU# in Hi-Z mode)
CPU-OD
Byte0, Bit 7
Byte0, Bit 0
0
1
0
1
Modes
Normal operation
Tri-state
Spread Spectrum On
Test mode (Spread Spectrum On)
Table 3
0
0
1
1
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